1# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk> 2# SPDX-License-Identifier: Apache-2.0 3 4# This binding aims for compatibility with the Linux devicetree binding: 5# https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt 6# https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml 7 8description: | 9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and 10 configurations in groups. Each group within the pinctrl node defines the pin multiplexing and 11 configuration for a peripheral, and each subgroup in the pin group defines all the pins for that 12 peripheral with the same configuration properties. Pins are selected either by named pin groups 13 (e.g. groups = "uart1_10_grp") or by named pins (e.g. pins = "MIO49") or a combination of 14 these. The remaining properties set configuration values for those pins. 15 16 Here is an example for UART1 pins: 17 18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h> 19 20 &pinctrl0 { 21 pinctrl_uart1_default: uart1-default { 22 mux { 23 groups = "uart1_10_grp"; 24 function = "uart1"; 25 }; 26 27 conf { 28 groups = "uart1_10_grp"; 29 slew-rate = <IO_SPEED_SLOW>; 30 power-source = <IO_STANDARD_LVCMOS18>; 31 }; 32 33 conf-rx { 34 pins = "MIO49"; 35 bias-high-impedance; 36 }; 37 38 conf-tx { 39 pins = "MIO48"; 40 bias-disable; 41 }; 42 }; 43 }; 44 45 See the Xilinx Zynq-7000 SoC Technical Reference Manual (UG585) for further details on pin 46 multiplexing and configuration options. 47 48compatible: "xlnx,pinctrl-zynq" 49 50include: base.yaml 51 52properties: 53 reg: 54 required: true 55 description: | 56 Base address and size of the System Level Control Registers (SLCR) space. 57 58 syscon: 59 type: phandle 60 required: true 61 description: | 62 phandle to the System Level Control Registers (SLCR). 63 64child-binding: 65 description: | 66 Xilinx Zynq 7000 SoC pin controller pin group 67 68 child-binding: 69 description: | 70 Xilinx Zynq 7000 SoC pin configuration node 71 72 include: 73 - name: pincfg-node.yaml 74 property-allowlist: 75 - bias-disable 76 - bias-high-impedance 77 - bias-pull-up 78 - low-power-enable 79 - low-power-disable 80 - power-source 81 - slew-rate 82 83 properties: 84 groups: 85 type: string-array 86 description: | 87 Specify list of pin groups to select for this configuration node. 88 89 Valid pin groups are "ethernet0_0_grp", "ethernet1_0_grp", "mdio0_0_grp," "mdio1_0_grp", 90 "qspi0_0_grp", "qspi1_0_grp", "qspi_fbclk," "qspi_cs1_grp", "spi0_0_grp", "spi0_1_grp", 91 "spi0_2_grp," "spi0_0_ss0", "spi0_0_ss1", "spi0_0_ss2", "spi0_1_ss0," "spi0_1_ss1", 92 "spi0_1_ss2", "spi0_2_ss0", "spi0_2_ss1," "spi0_2_ss2", "spi1_0_grp", "spi1_1_grp", 93 "spi1_2_grp," "spi1_3_grp", "spi1_0_ss0", "spi1_0_ss1", "spi1_0_ss2," "spi1_1_ss0", 94 "spi1_1_ss1", "spi1_1_ss2", "spi1_2_ss0," "spi1_2_ss1", "spi1_2_ss2", "spi1_3_ss0", 95 "spi1_3_ss1," "spi1_3_ss2", "sdio0_0_grp", "sdio0_1_grp", "sdio0_2_grp," "sdio1_0_grp", 96 "sdio1_1_grp", "sdio1_2_grp", "sdio1_3_grp," "sdio0_emio_wp", "sdio0_emio_cd", 97 "sdio1_emio_wp," "sdio1_emio_cd", "smc0_nor", "smc0_nor_cs1_grp," "smc0_nor_addr25_grp", 98 "smc0_nand", "can0_0_grp", "can0_1_grp," "can0_2_grp", "can0_3_grp", "can0_4_grp", 99 "can0_5_grp," "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp," "can0_10_grp", 100 "can1_0_grp", "can1_1_grp", "can1_2_grp," "can1_3_grp", "can1_4_grp", "can1_5_grp", 101 "can1_6_grp," "can1_7_grp", "can1_8_grp", "can1_9_grp", "can1_10_grp," "can1_11_grp", 102 "uart0_0_grp", "uart0_1_grp", "uart0_2_grp," "uart0_3_grp", "uart0_4_grp", "uart0_5_grp", 103 "uart0_6_grp," "uart0_7_grp", "uart0_8_grp", "uart0_9_grp", "uart0_10_grp," "uart1_0_grp", 104 "uart1_1_grp", "uart1_2_grp", "uart1_3_grp," "uart1_4_grp", "uart1_5_grp", "uart1_6_grp", 105 "uart1_7_grp," "uart1_8_grp", "uart1_9_grp", "uart1_10_grp", "uart1_11_grp," "i2c0_0_grp", 106 "i2c0_1_grp", "i2c0_2_grp", "i2c0_3_grp," "i2c0_4_grp", "i2c0_5_grp", "i2c0_6_grp", 107 "i2c0_7_grp," "i2c0_8_grp", "i2c0_9_grp", "i2c0_10_grp", "i2c1_0_grp," "i2c1_1_grp", 108 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp," "i2c1_5_grp", "i2c1_6_grp", "i2c1_7_grp", 109 "i2c1_8_grp," "i2c1_9_grp", "i2c1_10_grp", "ttc0_0_grp", "ttc0_1_grp," "ttc0_2_grp", 110 "ttc1_0_grp", "ttc1_1_grp", "ttc1_2_grp," "swdt0_0_grp", "swdt0_1_grp", "swdt0_2_grp", 111 "swdt0_3_grp," "swdt0_4_grp", "gpio0_0_grp", "gpio0_1_grp", "gpio0_2_grp," "gpio0_3_grp", 112 "gpio0_4_grp", "gpio0_5_grp", "gpio0_6_grp," "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", 113 "gpio0_10_grp," "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp," 114 "gpio0_15_grp", "gpio0_16_grp", "gpio0_17_grp", "gpio0_18_grp," "gpio0_19_grp", 115 "gpio0_20_grp", "gpio0_21_grp", "gpio0_22_grp," "gpio0_23_grp", "gpio0_24_grp", 116 "gpio0_25_grp", "gpio0_26_grp," "gpio0_27_grp", "gpio0_28_grp", "gpio0_29_grp", 117 "gpio0_30_grp," "gpio0_31_grp", "gpio0_32_grp", "gpio0_33_grp", "gpio0_34_grp," 118 "gpio0_35_grp", "gpio0_36_grp", "gpio0_37_grp", "gpio0_38_grp," "gpio0_39_grp", 119 "gpio0_40_grp", "gpio0_41_grp", "gpio0_42_grp," "gpio0_43_grp", "gpio0_44_grp", 120 "gpio0_45_grp", "gpio0_46_grp," "gpio0_47_grp", "gpio0_48_grp", "gpio0_49_grp", 121 "gpio0_50_grp," "gpio0_51_grp", "gpio0_52_grp", "gpio0_53_grp", "usb0_0_grp," "usb1_0_grp" 122 123 Pin groups are combined with pin names (see pins) to form the full list of pins to select. 124 125 pins: 126 type: string-array 127 description: | 128 Specify list of pin names to select for this configuration node. Valid pin names are 129 "MIO0" to "MIO53". 130 131 Pin names are combined with pin groups (see groups) to form the full list of pins to 132 select. 133 134 function: 135 type: string 136 enum: ["ethernet0", "ethernet1", "mdio0", "mdio1", "qspi0", "qspi1", "qspi_fbclk", 137 "qspi_cs1", "spi0", "spi0_ss", "spi1", "spi1_ss", "sdio0", "sdio0_pc", 138 "sdio0_cd", "sdio0_wp", "sdio1", "sdio1_pc", "sdio1_cd", "sdio1_wp", 139 "smc0_nor", "smc0_nor_cs1", "smc0_nor_addr25", "smc0_nand", "can0", 140 "can1", "uart0", "uart1", "i2c0", "i2c1", "ttc0", "ttc1", "swdt0", "gpio0", 141 "usb0", "usb1"] 142 description: | 143 Specify the alternative function to be configured for the given pin groups. Sets the 144 L3_SEL, L2_SEL, L1_SEL, and L0_SEL fields in the MIO_PIN_xx SLCR register. 145 146 bias-disable: 147 description: | 148 Disable any IO buffer pin bias. Clears the PULLUP and TRI_ENABLE fields in the MIO_PIN_xx 149 SLCR register. 150 151 bias-high-impedance: 152 description: | 153 Enables tri-state on IO buffer pin. Sets the TRI_ENABLE field in the MIO_PIN_xx SLCR 154 register. 155 156 bias-pull-up: 157 description: | 158 Enables pull-up on IO buffer pin. Sets the PULLUP field in the MIO_PIN_xx SLCR register. 159 160 low-power-enable: 161 description: | 162 Disable HSTL input buffer to save power when it is an output-only. Applicable when 163 power-source (IO_Type) is HSTL. Sets the DisableRcvr field in the MIO_PIN_xx SLCR 164 register. 165 166 low-power-disable: 167 description: | 168 Enable HSTL input buffer. Applicable when the power-souce (IO_Type) is HSTL. Clears the 169 DisableRcvr field in the MIO_PIN_xx SLCR register. 170 171 power-source: 172 enum: [1, 2, 3, 4] 173 description: | 174 IO buffer type. Sets the IO_Type field in the MIO_PIN_xx SLCR register. The IO_STANDARD_* 175 macros are defined in pinctrl-zynq.h. 176 177 1 or IO_STANDARD_LVCMOS18 178 2 or IO_STANDARD_LVCMOS25 179 3 or IO_STANDARD_LVCMOS33 180 4 or IO_STANDARD_HSTL 181 182 slew-rate: 183 enum: [0, 1] 184 description: | 185 IO buffer edge rate. Applicable when the power-source (IO_type) is LVCMOS18, LVCMOS25, or 186 LVCMOS33. Sets the Speed field in the MIO_PIN_xx SLCR register. The IO_SPEED_* macros are 187 defined in pinctrl-zynq.h. 188 189 0 or IO_SPEED_SLOW 190 1 or IO_SPEED_FAST 191
