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Searched +full:tx +full:- +full:invert (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.5.0/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
7 include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
22 single-wire:
25 Enable the single wire half-duplex communication.
26 Using this mode, TX and RX lines are internally connected and
27 only TX pin is used afterwards and should be configured.
28 RX/TX conflicts must be handled on user side.
30 tx-rx-swap:
33 Swap the TX and RX pins. Used in case of a cross wired connection.
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Di2s.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for the I2S (Inter-IC Sound) bus drivers.
18 * @brief I2S (Inter-IC Sound) Interface
21 * as common non-standard extensions such as PCM Short/Long Frame Sync,
53 * -. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-.
54 * SCK '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '
55 * -. .-------------------------------.
56 * WS '-------------------------------' '----
57 * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.
59 * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'
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Dlora.h4 * SPDX-License-Identifier: Apache-2.0
40 * @brief LoRa data-rate
73 /** The data-rate to use for transceiving */
82 /** TX-power in dBm to use for transmission */
86 bool tx; member
89 * Invert the In-Phase and Quadrature (IQ) signals. Normally this
90 * should be set to false. In advanced use-cases where a
98 * Sets the sync-byte to use:
99 * - false: for using the private network sync-byte
100 * - true: for using the public network sync-byte
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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Dnrf-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..16: Pin function.
14 * - 15: Reserved.
15 * - 14: Pin inversion mode.
16 * - 13: Pin low power mode.
17 * - 12..9: Pin output drive configuration.
18 * - 8..7: Pin pull configuration.
19 * - 6..0: Pin number (combination of port and pin).
31 /** Position of the invert field. */
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/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_intel.c2 * Copyright (c) 2018-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
93 ((const struct gpio_intel_config *)(_dev)->config)
94 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
140 struct gpio_intel_data *data = dev->data; in check_perm()
141 const struct gpio_intel_config *cfg = dev->config; in check_perm()
144 pin_offset = cfg->pin_offset; in check_perm()
160 offset = data->pad_base + (raw_pin << 4); in check_perm()
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/Zephyr-Core-3.5.0/scripts/utils/
Dpinctrl_nrf_migrate.py4 # SPDX-License-Identifier: Apache-2.0
11 nRF-based boards using the old <signal>-pin properties to select peripheral
13 file by removing old pin-related properties replacing them with pinctrl states.
14 A board-pinctrl.dtsi file will be generated containing the configuration for
28 -i path/to/board.dts
29 [--no-backup]
30 [--skip-nrf-check]
31 [--header ""]
35 .. code-block:: devicetree
41 tx-pin = <5>;
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
225 * Added support for the full ISO TX data path, including ISOAL
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
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