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/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
[all …]
/Zephyr-Core-3.5.0/boards/arm/arty/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
16 /* Use DTCM as SRAM by default */
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
105 compatible = "gpio-keys";
149 compatible = "arm,daplink-qspi-mux";
151 interrupt-parent = <&nvic>;
[all …]
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
80 _ier = *reg_enable[IT8XXX2_IER_COUNT - 1]; in ite_intc_save_and_disable_interrupts()
125 /* critical section due to run a bit-wise OR operation */ in ite_intc_irq_enable()
144 /* critical section due to run a bit-wise OR operation */ in ite_intc_irq_disable()
158 volatile uint8_t *tri; in ite_intc_irq_polarity_set() local
165 tri = reg_ipolr[g]; in ite_intc_irq_polarity_set()
167 CLEAR_MASK(*tri, BIT(i)); in ite_intc_irq_polarity_set()
169 SET_MASK(*tri, BIT(i)); in ite_intc_irq_polarity_set()
171 tri = reg_ielmr[g]; in ite_intc_irq_polarity_set()
173 CLEAR_MASK(*tri, BIT(i)); in ite_intc_irq_polarity_set()
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_xlnx_axi.c4 * SPDX-License-Identifier: Apache-2.0
54 uint32_t tri; member
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
89 struct gpio_xlnx_axi_data *data = dev->data; in gpio_xlnx_axi_pin_configure()
[all …]
Dgpio_ite_it8xxx2_v2.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
18 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
69 const struct gpio_ite_cfg *gpio_config = dev->config; in gpio_ite_configure()
70 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr; in gpio_ite_configure()
71 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr; in gpio_ite_configure()
72 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr; in gpio_ite_configure()
73 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin; in gpio_ite_configure()
74 struct gpio_ite_data *data = dev->data; in gpio_ite_configure()
80 return -ENOTSUP; in gpio_ite_configure()
[all …]
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
77 (volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) : in wuesr()
78 (volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5)); in wuesr()
82 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dnuvoton,npcx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
15 - pinmux-locked: Lock pinmux configuration for peripheral device
16 - pinmux-gpio: Inverse pinmux back to gpio
17 - psl-in-mode: Select the assertion detection mode of PSL input
18 - psl-in-pol: Select the assertion detection polarity of PSL input
23 #include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
26 internal 3.3V pull-up if its i2c frequency won't exceed 400kHz.
[all …]
Dxlnx,pinctrl-zynq.yaml2 # SPDX-License-Identifier: Apache-2.0
5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
21 pinctrl_uart1_default: uart1-default {
29 slew-rate = <IO_SPEED_SLOW>;
30 power-source = <IO_STANDARD_LVCMOS18>;
33 conf-rx {
35 bias-high-impedance;
[all …]
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_xlnx_axi_quadspi.c4 * SPDX-License-Identifier: Apache-2.0
98 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read32()
100 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
107 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_write32()
109 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
114 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_cs_control()
115 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_cs_control()
116 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_cs_control()
117 uint32_t spissr = BIT_MASK(config->num_ss_bits); in xlnx_quadspi_cs_control()
120 /* Skip slave select assert/de-assert in slave mode */ in xlnx_quadspi_cs_control()
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
146 malt1 = regs->MODE_ALT1; in qmspi_reset()
[all …]
Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
57 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
62 return REG8(&regs->RX_FIFO); in rxb_rd8()
86 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
88 regs->MODE = qmode; in qmspi_set_frequency()
128 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
134 regs->MODE = (regs->MODE & ~(MCHP_QMSPI_M_SIG_MASK)) in qmspi_set_signalling_mode()
147 switch (config->operation & SPI_LINES_MASK) { in qmspi_config_get_lines()
161 default: in qmspi_config_get_lines()
178 const struct spi_qmspi_config *cfg = dev->config; in qmspi_configure()
[all …]
/Zephyr-Core-3.5.0/subsys/mgmt/osdp/
DKconfig.pd4 # SPDX-License-Identifier: Apache-2.0
11 default 1
18 default 16
26 default 1
38 default "NONE"
43 channel with default SCBK. Once as secure channel is active with the
44 default key, the CP can send a KEYSET command to set new keys to the PD.
54 default 0x001A2B3C
61 default 1
68 default 1
[all …]
/Zephyr-Core-3.5.0/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
50 * KSO push-pull/open-drain bit of KSO[15:0] control register
71 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
72 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
73 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
74 uint8_t pin = pins->pin; in pinctrl_it8xxx2_set()
75 volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin; in pinctrl_it8xxx2_set()
76 volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]); in pinctrl_it8xxx2_set()
78 /* Setting pull-up or pull-down. */ in pinctrl_it8xxx2_set()
81 /* No pull-up or pull-down */ in pinctrl_it8xxx2_set()
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Dsoc_espi_saf_v1.h4 * SPDX-License-Identifier: Apache-2.0
34 /* Default SAF Map of eSPI TAG numbers to master numbers */
40 * Default QMSPI clock divider and chip select timing.
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
106 /* SAF Pre-fetch optimization mode */
112 * SAF Opcode 32-bit register value.
113 * Each byte contain a SPI flash 8-bit opcode.
117 * op0 = SPI flash write-enable opcode
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
33 /* Default SAF Map of eSPI TAG numbers to master numbers */
39 * Default QMSPI clock divider and chip select timing.
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
130 /* SAF Pre-fetch optimization mode */
136 * SAF Opcode 32-bit register value.
137 * Each byte contain a SPI flash 8-bit opcode.
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso11u68/doc/
Dindex.rst10 on an ARM Cortex-M0+ core.
21 - LPC11U68 microcontroller in LQFP100 package
22 - ARM Cortex-M0+
23 - Memory:
25 - 256KB of flash memory
26 - 32KB of SRAM
27 - 2x2KB of additional SRAM
28 - 4 KB EEPROM
29 - USB:
31 - USB 2.0 Full-Speed device controller
[all …]
/Zephyr-Core-3.5.0/boards/arm/frdm_kl25z/doc/
Dindex.rst3 NXP FRDM-KL25Z
9 The Freedom KL25Z is an ultra-low-cost development platform for
11 on ARM |reg| Cortex |reg|-M0+ processor.
13 The FRDM-KL25Z features include easy access to MCU I/O, battery-ready,
14 low-power operation, a standard-based form factor with expansion board
15 options and a built-in debug interface for flash programming and run-control.
20 :alt: FRDM-KL25Z
25 - MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP
26 - On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED
27 - OpenSDA debug interface
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso51u68/doc/
Dindex.rst10 on an ARM CORTEX-M0+ core.
19 - LPC51U68 M0+ running at up to 150 MHz
20 - Memory
22 - 256KB of flash memory
23 - 96KB of SRAM
24 - On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol
25 support, can debug the on-board LPC51U68 or an external target
26 - External debug probe option
27 - Tri-color LED, target reset, ISP & interrupt/user buttons for easy testing of
29 - Expansion options based on Arduino UNO and PMOD™, plus additional expansion
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s06/doc/
Dindex.rst10 of the LPC55S0x/LPC550x MCU family, based on the Arm® Cortex®-M33
23 - LPC55S06 Arm® Cortex®-M33 microcontroller running at up to 96 MHz
24 - 256 KB flash and 96 KB SRAM on-chip
25 - LPC-Link2 debug high speed USB probe with VCOM port
26 - MikroElektronika Click expansion option
27 - LPCXpresso expansion connectors compatible with Arduino UNO
28 - PMod compatible expansion / host connector
29 - Reset, ISP, wake, and user buttons for easy testing of software functionality
30 - Tri-color LED
31 - UART header for external serial to USB cable
[all …]
/Zephyr-Core-3.5.0/boards/arm/frdm_k82f/doc/
Dindex.rst3 NXP FRDM-K82F
9 The FRDM-K82F is a low-cost development platform for Kinetis K80, K81,
12 - Form-factor compatible with the Arduino R3 pin layout
13 - Peripherals enable rapid prototyping, including a six-axis digital
15 tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb
17 with Bluetooth and 2.4 GHz radio add-on modules
18 - OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter
20 flash programming, and run-control debugging
24 :alt: FRDM-K82F
29 - MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power,
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso54114/doc/
Dindex.rst10 prototyping with the low-power LPC54110 family of MCUs. LPCXpresso* is a
11 low-cost development platform available from NXP supporting NXP's ARM-based
12 microcontrollers. LPCXpresso is an end-to-end solution enabling embedded
23 - LPC54114 dual-core (M4F and dual M0) MCU running at up to 100 MHz
24 - On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol
25 support, can debug the on-board LPC54114 or an external target
26 - External debug probe option
27 - Tri-color LED, target Reset, ISP & interrupt/user buttons for easy testing of
29 - Expansion options based on Arduino UNO and Pmod™, plus additional expansion
31 - On-board 1.8 V and 3.3 V regulators plus external power supply option
[all …]
/Zephyr-Core-3.5.0/scripts/kconfig/
Dguiconfig.py4 # SPDX-License-Identifier: ISC
10 # pylint: disable=undefined-variable
16 A Tkinter-based menuconfig implementation, based around a treeview control and
21 single menu (like menuconfig.py). Only single-menu mode distinguishes between
24 A show-all mode is available that shows invisible items in red.
29 Ctrl-S : Save configuration
30 Ctrl-O : Open configuration
31 Ctrl-A : Toggle show-all mode
32 Ctrl-N : Toggle show-name mode
33 Ctrl-M : Toggle single-menu mode
[all …]
/Zephyr-Core-3.5.0/boards/arm/frdm_k22f/doc/
Dindex.rst3 NXP FRDM-K22F
9 The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22
12 - Form-factor compatible with the Arduino R3 pin layout
13 - Peripherals enable rapid prototyping, including a 6-axis digital
15 tri-colored LED and 2 user push-buttons for direct interaction, a optional
17 add-on modules
18 - OpenSDAv2, the NXP open source hardware embedded serial and debug adapter
20 flash programming, and run-control debugging
24 :alt: FRDM-K22F
29 - MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power,
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s16/doc/
Dindex.rst10 of the LPC55S1x/LPC551x MCU family, based on the Arm® Cortex®-M33
23 - LPC55S16 Arm® Cortex®-M33 microcontroller running at up to 150 MHz
24 - 256 KB flash and 96 KB SRAM on-chip
25 - LPC-Link2 debug high speed USB probe with VCOM port
26 - I2C and SPI USB bridging to the LPC device via LPC-Link2 probe
27 - MikroElektronika Click expansion option
28 - LPCXpresso expansion connectors compatible with Arduino UNO
29 - PMod compatible expansion / host connector
30 - Reset, ISP, wake, and user buttons for easy testing of software functionality
31 - Tri-color LED
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s36/doc/
Dindex.rst10 of the LPC55S3x/LPC553x MCU family, based on the Arm® Cortex®-M33
23 - LPC55S36 Arm® Cortex®-M33 microcontroller running at up to 150 MHz
24 - 256 KB flash and 96 KB SRAM on-chip
25 - LPC-Link2 debug high speed USB probe with VCOM port
26 - I2C and SPI USB bridging to the LPC device via LPC-Link2 probe
27 - MikroElektronika Click expansion option
28 - LPCXpresso expansion connectors compatible with Arduino UNO
29 - PMod compatible expansion / host connector
30 - Reset, ISP, wake, and user buttons for easy testing of software functionality
31 - Tri-color LED
[all …]

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