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/Zephyr-latest/tests/boards/native_sim/rtc/src/
Dmain.c42 #define TOLERANCE 20 /* ms Tolerance in native_posix time after WAIT_TIME */ macro
100 TOLERANCE); in ZTEST()
102 zassert_true(llabs(error) < TOLERANCE, in ZTEST()
103 "Real time error over TOLERANCE"); in ZTEST()
120 zassert_true(llabs(error) < TOLERANCE, in ZTEST()
121 "PSEUDOHOSTREALTIME time error over TOLERANCE"); in ZTEST()
159 zassert_true(llabs(error) < TOLERANCE, in ZTEST()
160 "PSEUDOHOSTREALTIME offset error over TOLERANCE"); in ZTEST()
/Zephyr-latest/tests/arch/common/timing/src/
Dmain.c25 #define TOLERANCE 0.1 macro
53 zassert_within(diff1, diff2, diff1 * TOLERANCE, NULL); in perform_tests()
54 zassert_within(diff_all, diff1 + diff2, (diff1 + diff2) * TOLERANCE, in perform_tests()
66 zassert_within(diff1_ns, WAIT_NS, WAIT_NS * TOLERANCE, NULL); in perform_tests()
67 zassert_within(diff2_ns, WAIT_NS, WAIT_NS * TOLERANCE, NULL); in perform_tests()
68 zassert_within(diff_all_ns, 2 * WAIT_NS, 2 * WAIT_NS * TOLERANCE, NULL); in perform_tests()
71 zassert_within(diff_avg_ns, WAIT_NS, WAIT_NS * TOLERANCE, NULL); in perform_tests()
/Zephyr-latest/tests/boards/nrf/coresight_stm/pytest/
Dtest_stm.py46 tolerance: float | None
111 threshold = cfg[check]["expected"] * (1 + constraints.tolerance)
194 tolerance=0.5, # 50 %
205 tolerance=0.5,
216 tolerance=0.5,
227 tolerance=0.5,
277 tolerance=0.5, # 50 %
288 tolerance=0.5,
299 tolerance=0.5,
310 tolerance=0.5, # 50 %
/Zephyr-latest/tests/subsys/portability/cmsis_rtos_v1/src/
Dkernel_apis.c13 /* Specify accepted tolerance. On some Zephyr platforms (e.g. nRF5x) the busy
19 /* High frequency clock used for k_busy_wait may have up to 8% tolerance.
20 * Additionally, if RC is used for low frequency clock then it has 5% tolerance.
/Zephyr-latest/drivers/mspi/
DKconfig35 int "Completion timeout tolerance (ms)"
38 The tolerance value in ms for the MSPI completion timeout logic.
/Zephyr-latest/tests/drivers/regulator/voltage/dts/bindings/
Dtest-regulator-voltage.yaml25 tolerance-microvolt:
29 Tolerance (+/-) when reading configured voltages using ADC. This should
/Zephyr-latest/tests/drivers/regulator/voltage/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay41 * a voltage within given tolerance
45 tolerance-microvolt = <35000>, <35000>;
Dlpcxpresso55s36.overlay15 tolerance-microvolt = <1000000>;
Dfrdm_mcxn947_mcxn947_cpu0.overlay16 tolerance-microvolt = <10000>;
Dfrdm_mcxn947_mcxn947_cpu0_qspi.overlay16 tolerance-microvolt = <10000>;
Dfrdm_mcxn236.overlay16 tolerance-microvolt = <10000>;
Drpi_pico.overlay19 tolerance-microvolt = <50000>;
Dfrdm_mcxw71.overlay16 tolerance-microvolt = <40000>;
Dnrf52840dk_nrf52840_npm6001.overlay17 tolerance-microvolt = <75000>, <25000>, <25000>, <75000>,
/Zephyr-latest/tests/kernel/sched/schedule_api/src/
Dtest_sched_timeslice_reset.c25 /* Task switch tolerance ... */
30 /* ... 1ms is faster than a tick, loosen tolerance to 1 tick */
60 * expected to switch in less than the switching tolerance. in thread_time_slice()
71 * also expecting task switch below the switching tolerance. in thread_time_slice()
/Zephyr-latest/drivers/spi/
DKconfig63 int "Completion timeout tolerance (ms)"
66 The tolerance value in ms for the SPI completion timeout logic.
/Zephyr-latest/dts/bindings/led_strip/
Dws2812.yaml31 There is a +/- 80 ns tolerance for each timing.
/Zephyr-latest/include/zephyr/drivers/
Demul_sensor.h88 * @brief Query an emulator for a channel's supported sample value range and tolerance
94 * @param[out] epsilon Tolerance to use comparing expected and actual values to account for rounding
/Zephyr-latest/tests/drivers/regulator/voltage/src/
Dmain.c57 TC_PRINT("Testing %s, %u voltage/s (tolerance: %d uV)\n", in ZTEST()
/Zephyr-latest/include/zephyr/drivers/pcie/
Dcap.h78 #define PCIE_EXT_CAP_ID_LTR 0x0018U /**< Latency Tolerance Reporting */
/Zephyr-latest/dts/bindings/regulator/
Dregulator.yaml88 voltage, plus/minus whatever tolerance the board design requires. This
/Zephyr-latest/scripts/tests/twister_blackbox/
Dtest_runner.py550 tolerance = 1.0
563 elapsed_time - float(timeout) * 10) <= tolerance, f"Time is different from expected"
/Zephyr-latest/drivers/pcie/host/
Dshell.c74 { PCIE_EXT_CAP_ID_LTR, "Latency Tolerance Reporting" },
/Zephyr-latest/tests/kernel/timer/timer_api/src/
Dmain.c27 * tolerance interval.
726 * As above, use higher tolerance on platforms where the clock used in ZTEST_USER()
/Zephyr-latest/doc/kernel/
Dtimeutil.rst194 timer with 5% tolerance).

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