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/hal_intel-latest/docs/
Dbsp_sedi_doxyfile3 # This file describes the settings to be used by the documentation system
37 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
52 # the logo to the output directory.
56 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
58 # entered, it will be relative to the location where doxygen was started. If
63 # If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
73 # If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
74 # characters to appear in the names of generated files. If set to NO, non-ASCII
81 # The OUTPUT_LANGUAGE tag is used to specify the language in which all
83 # information to generate all constant output in the proper language.
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/hal_intel-latest/bsp_sedi/include/driver/
Dsedi_driver_uart.h130 /** de to re turnaround time in nanoseconds. */
133 /** re to de turnaround time in nanoseconds. */
204 uint32_t data_len; /**< Number of bytes to transfer. */
211 * @param[in] status UART module status.To be interpreted with
236 sedi_uart_io_vec_t *vec; /* Pointer to vector of transfers */
262 sedi_dma_t dma_dev; /**< Dma device to be used. */
263 int32_t channel; /**< Dma channel number to be used. */
286 * @param[in] uart Which UART module to configure.
302 * to guarantee that the UART interface is available.
304 * @param[in] uart Which UART to read the status of.
[all …]
Dsedi_driver_hpet.h76 * Or interrupt might be missed due to the hardware latency
83 * \param[in] clk_divisor: the clock divisor to set.
84 * \param[in] min_delay: SoC-specific HPET minimal delay time to set.
97 * \param[in] state: the power state to be set to the device
103 * \brief Set the timer's comparator. This means when to trigger an interrupt.
104 * \param[in] timer_id: Timer ID to set.
105 * \param[in] value: The value need to set.
111 * \brief Set the timer's main counter to the new value.
112 * \param[in] value: The value need to set.
126 * \param[in] timer_id: Timer ID to enable interrupt.
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Dsedi_driver_spi.h53 * No need to input args
59 * Need to input microwire configure pointer
66 * For 4 bits operation, users need to provide an expand buffer, which
67 * covert 4-bits data to 8-bits data. The transfer size shall also use
85 * SPI slave's CS pin to a fixed low level.
133 * Set the dummy data on the bus, for example, master wants to read
151 * not physical continuous. Users need to update buffer while callback
153 * Users need to use function sedi_spi_update_tx_buf or
154 * sedi_spi_update_rx_buf to update buffers.
242 * it transfer data, see sedi_spi_capabilities to get if hw support it.
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Dsedi_driver_i2c.h57 * \brief Control function parameter, set DMA memory type, only used to tell
64 * \brief Control function parameter, set DMA memory type, only used to tell
344 * \param[in] state: the power state to be set to the device
351 * \brief Start transmitting data to i2c slave device as master
355 * which need write to the slave
356 * \param[in] num: number of data bytes to transfer
370 * \param[out] num: number of data bytes to receive
380 * \brief Start transmitting data to i2c slave device as master
385 * which need write to the slave
386 * \param[in] num: number of data bytes to transfer
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Dsedi_driver_ipc.h146 * write CSR message to peer.
148 * param[in] csr: the csr content to sent
181 * param[in] state: the power state to be set to the device
188 * Write data to IPC message fifo
190 * param[in] msg: point to memory area where data is stored
208 * param[out] msg: point to memory area where data will be stored
218 * param[out] doorbel: point to the value of doorbell
244 * param[out] doorbell: the buffer to store ack msg
Dsedi_driver_dma.h80 DMA_MEMORY_TO_MEMORY = 0x0, /**< Memory to memory transfer. */
81 DMA_MEMORY_TO_PERIPHERAL = 0x1, /**< Memory to peripheral transfer.*/
82 DMA_PERIPHERAL_TO_MEMORY = 0x2, /**< Peripheral to memory transfer. */
83 DMA_PERIPHERAL_TO_PERIPHERAL = 0x3, /**< Peripheral to peripheral. */
152 /**< Pointer to next LLI. */
331 * \param[in] state: the power state to be set to the device
360 * \param[inout] ll_p: linked list pointer to fill up
365 * \param[in] ll_p_next: the pointer to next node, set NULL for the last one
375 * \param[inout] ll_p: linked list pointer to fill up
Dsedi_driver_gpio.h182 * \param[in] state: the power state to be set to the device
202 * \param[in] pin_state: pin state value to write
212 * \param[in] pin_state: pin state value to write
222 * \param[in] pin_state: pin state value to write
232 * \param[in] pin_state: pin state value to write
303 * \param[in] val: Clear mask value, any bit equals to 1 means clear the
313 * \param[in] val: Clear mask value, any bit equals to 1 means clear the
Dsedi_driver_pm.h30 * \param[in] state: the power state to be set to the device
43 * \brief Notify host suspend state change to SEDI PM
/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c11 * Due to very limit AON memory size (typically total 8KB), we don't want to
25 * Indicate completion of servicing the interrupt to IOAPIC first in pmu_wakeup_isr()
26 * then indicate completion of servicing the interrupt to LAPIC in pmu_wakeup_isr()
43 * Indicate completion of servicing the interrupt to IOAPIC first in reset_prep_isr()
44 * then indicate completion of servicing the interrupt to LAPIC in reset_prep_isr()
59 * vector number, for IDT header, the 'start' filed still need to point to
123 * TSS's limit specified as 0x67, to allow the task has permission to
125 * must be greater than or equal to TSS' limit
223 /* store main FW's read and write data region to IMR/UMA DDR */ in store_main_fw()
312 /* SRAM needs time to enter retention mode */
[all …]
Dipapg.S94 #we didn't go through ROM, clear PG_EN bit and return an abort condition to AON
100 #return to caller that we got ouf of PG
106 #return to AON task (still with ROM GDT and segments in case of PG exit)
Daon_share.h47 * address need 64 bytes align due to DMA requirement
54 * address need 64 bytes align due to DMA requirement
/hal_intel-latest/zephyr/iut_test/test_zephyr/gpio/
Dtest_gpio.c43 iut_case_print("starting to test gpio pin %d output ...\n", i); in test_gpio_output()
45 /* Configure gpio pin to output mode, set to high */ in test_gpio_output()
51 /* Set pin to input mode and check the level */ in test_gpio_output()
57 /* Set pin to output and set to low */ in test_gpio_output()
63 /* Set pin to input mode and check the level */ in test_gpio_output()
/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/
Dish_dma.c17 * The timeout is approximately 2.2 seconds according to in dma_poll()
90 * shut off interrupts to assure no simultanious in ish_dma_copy()
91 * access to DMA registers in ish_dma_copy()
95 write32(MISC_CHID_CFG_REG, chan); /* Set channel to configure */ in ish_dma_copy()
121 write32(MISC_CHID_CFG_REG, chan); /* Set channel to configure */ in ish_dma_copy()
122 write32(DMA_CTL_HIGH(chan_reg), chunk); /* Set number of bytes to transfer */ in ish_dma_copy()
151 /* Write 0 to channel enable bit ... */ in ish_dma_disable()
176 write32(MISC_CHID_CFG_REG, chan); /* Set channel to configure */ in ish_dma_set_msb()
Dish_pm.c89 * To keep LPM fucntions intact and still support both edge configuration,
91 * Before entering LPM, scan all gpio pins which are configured to be
92 * triggered by both-edge, and temporarily set each gpio pin to the single
93 * edge expected to be triggered next time, that is, opposite to its value.
102 * scan GPIO GFER, GRER and GIMR registers to find the both edge in convert_both_edge_gpio_to_single_edge()
134 /* point to the aon shared data in aontask */
199 /* add the new entry descriptor to the GDT */ in add_gdt_entry()
313 /* switch to aontask through a far call with aontask's TSS selector */ in switch_to_aontask()
570 * Indicate completion of servicing the interrupt to IOAPIC in handle_d3()
572 * to LAPIC in handle_d3()
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Dia_structs.h38 struct gdt_entry *entries; /* pointer to GDT entries */
52 uint8_t zero; /* must be set to zero */
62 struct idt_entry *entries; /* pointer to IDT entries */
Dish_pm.h30 * similar to D0I3, but will reset ISH
57 * ISH HW looks at the rising edge of this bit to in ish_mia_reset()
/hal_intel-latest/bsp_sedi/drivers/spi/
Dsedi_spi_dw_apb.c40 * SPI Control Register is valid only when SSI_SPI_MODE is either set to
233 /* DFS: Data Frame size only valid when SSI_MAX_XFER_SIZE is configured to in lld_spi_default_config()
234 * 16, if SSI_MAX_XFER_SIZE is configured to 32, then writing to this field in lld_spi_default_config()
236 * DFS_32: only valid when SSI_MAX_XFER_SIZE is configured to 32 in lld_spi_default_config()
293 /* DFS: Data Frame size only valid when SSI_MAX_XFER_SIZE is configured to in lld_spi_config_width()
294 * 16, if SSI_MAX_XFER_SIZE is configured to 32, then writing to this field in lld_spi_config_width()
296 * DFS_32: only valid when SSI_MAX_XFER_SIZE is configured to 32 in lld_spi_config_width()
324 /* Set to receive only mode */ in lld_spi_set_transfer_mode()
328 /* Set to transmit only mode */ in lld_spi_set_transfer_mode()
346 /* In quad mode, need to send opcode and addr first */ in lld_spi_fill_fifo()
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/hal_intel-latest/bsp_sedi/soc/common/include/
Dsedi_ipc_regs.h22 * PISR_AGENT2ISH: Peripheral Interrupt Status - IRQ to ISH
77 * PIMR_AGENT2ISH: Peripheral Interrupt Mask - IRQ to ISH
154 * PIMR_ISH2AGENT: Peripheral Interrupt Mask - IRQ to AGENT
209 * PISR_ISH2AGENT: Peripheral Interrupt Status - IRQ to AGENT
372 * AGENT2ISH_DOORBELL_AGENT: Inbound Doorbell AGENT To ISH
405 * ISH2AGENT_DOORBELL_AGENT: Outbound DoorbellISH To AGENT
438 * ISH2AGENT_MSG_AGENT: Outbound Inter Processor Message 1 From ISH To AGENT
448 * MSG: Outbound message register from ISH to AGENT
459 * AGENT2ISH_MSG_AGENT: Inbound Inter Processor Message 1 From AGENT To ISH
469 * MSG: Inbound message register from AGENT to ISH
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/hal_intel-latest/bsp_sedi/drivers/usart/
Dsedi_dw_uart.c31 /* Change TX Threshold to empty, keep RX Threshold to default. */
38 /* SCR bit to indicate updated status for LSR. */
72 /* Packs the assertion and deassertion time to a uint32_t. */
78 /* Packs the de to re and re to de times to a uint32_t. */
86 * UART context to be saved between sleep/resume.
89 * This structure is only intended to be used by the sedi_uart_save_context and
132 /* Buffer pointers to store transmit / receive data for UART. */
188 /* DMA driver requires to have a callback to be provided during init even
226 /* wait for transfer to complete as data may in sedi_dma_event_cb()
290 /* Set active xfer to false. */ in io_vec_write_callback()
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/hal_intel-latest/
DLICENSE12 may be used to endorse or promote products derived from this software
16 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
DSECURITY.md5 Please report security issues or vulnerabilities to the [Intel Security Center].
7 For more information on how Intel works to resolve security issues, see
/hal_intel-latest/bsp_sedi/drivers/i2c/
Dsedi_i2c_dw_apb_200a.c440 /* No need to send anymore */ in i2c_ask_data()
453 /* To prevent RX FIFO overflow, need to make sure command number less in i2c_ask_data()
529 /* NO need to send STOP, but need to change watermark in i2c_send()
530 * to 0, this will have a interrupt while all data sent out in i2c_send()
555 /* Used for I2C DMA Rx, peripheral to peripheral not support, from has 5.8 */
673 /* DMA error, go to end */ in callback_dma_transfer()
867 /* If less than half FIFO, just set watermark to transfer size in sedi_i2c_master_write_async()
880 /* Reset event to default */ in sedi_i2c_master_write_async()
921 /* If less than half FIFO, just set watermark to transfer size in sedi_i2c_master_read_async()
935 /* Reset event to default */ in sedi_i2c_master_read_async()
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/hal_intel-latest/zephyr/iut_test/test_zephyr/i2c/
Dtest_i2c_log.c129 iut_case_print("starting to run %d seconds ...\n", sec_run); in test_log_i2c_polling()
150 iut_case_print("starting to run %d seconds ...\n", sec_run); in test_log_i2c_irq()
176 iut_case_print("starting to run %d seconds ...\n", sec_run); in test_log_i2c_async()
/hal_intel-latest/bsp_sedi/drivers/gpio/
Dsedi_gpio.c59 /* gpio instance to source mapping*/
81 /* Do nothing now, need to use gpio as wake up */ in gpio_set_power()
219 /* Set all registers to default state */ in sedi_gpio_init()
226 /* Set flag to init */ in sedi_gpio_init()
247 /* Set all registers to default state */ in sedi_gpio_uninit()

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