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/Zephyr-latest/dts/bindings/sensor/
Dti,ina237.yaml4 # SPDX-License-Identifier: Apache-2.0
9 The <zephyr/dt-bindings/sensor/ina237.h> file should be included in the
15 include: ti,ina23x-common.yaml
24 e.g shunt voltage and bus voltage ADC conversion
26 delay for initial ADC conversion, shunt full scale range
31 adc-config:
36 Value of the ADC configuration register (ADC conversion times,
41 alert-config:
43 description: Diag alert register, default matches the power-on reset value
45 adc-mode:
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/Zephyr-latest/drivers/sensor/hp206c/
Dhp206c.c5 * SPDX-License-Identifier: Apache-2.0
26 const struct hp206c_device_config *cfg = dev->config; in hp206c_bus_config()
31 return i2c_configure(cfg->i2c.bus, i2c_cfg); in hp206c_bus_config()
37 const struct hp206c_device_config *cfg = dev->config; in hp206c_read()
41 if (i2c_burst_read_dt(&cfg->i2c, cmd, data, len) < 0) { in hp206c_read()
42 return -EIO; in hp206c_read()
59 const struct hp206c_device_config *cfg = dev->config; in hp206c_write()
63 if (i2c_burst_write_dt(&cfg->i2c, cmd, data, len) < 0) { in hp206c_write()
64 return -EIO; in hp206c_write()
80 const struct hp206c_device_config *cfg = dev->config; in hp206c_cmd_send()
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/Zephyr-latest/drivers/timer/
Dmchp_mec5_ktimer.c3 * SPDX-License-Identifier: Apache-2.0
49 * To reduce truncation errors from accumulating due to conversion
50 * to/from time, ticks, and HW cycles set ticks per second equal to
58 /* Mask off bits[31:28] of 32-bit count */
101 * This synchronization can take from nearly 0 time up to 1 32KHz clock as it
103 * was on. We detect the timer is in the load state by checking the read-only
121 static uint32_t last_announcement; /* last time we called sys_clock_announce() */
130 * RTMR counter register is read-only and is loaded from the preload
131 * register by a 0->1 transition of the control register start bit.
139 uint32_t ccr, temp; in sys_clock_set_timeout() local
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Dmchp_xec_rtos_timer.c4 * SPDX-License-Identifier: Apache-2.0
46 * To reduce truncation errors from accumulating due to conversion
47 * to/from time, ticks, and HW cycles set ticks per second equal to
67 * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,
77 /* Mask off bits[31:28] of 32-bit count */
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()
136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()
141 TIMER_REGS->CTRL = 0U; in timer_restart()
142 TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN; in timer_restart()
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/Zephyr-latest/dts/arm/st/g0/
Dstm32g0.dtsi3 * Copyright (c) 2019-2024 STMicroelectronics
6 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
8 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv6-m.dtsi>
12 #include <zephyr/dt-bindings/clock/stm32g0_clock.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/adc.h>
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/Zephyr-latest/doc/releases/
Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
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Drelease-notes-2.1.rst13 * Expanded support for ARMv6-M architecture.
50 hardware-based stack overflow detection) in ARMv6-M architecture
51 * Added QEMU support for ARMv6-M architecture
52 * Extended test coverage for ARM-specific kernel features in ARMv6-M
54 * Enhanced runtime MPU programming in ARMv8-M architecture, making
55 the full partitioning of kernel SRAM memory a user-configurable
57 * Added CMSIS support for Cortex-R architectures.
59 * Added missing Cortex-R CPU device tree bindings.
60 * Fixed incorrect Cortex-R device tree specification.
68 * RISC-V:
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