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/Zephyr-latest/doc/project/
Dcode_flow.rst1 .. _code-flow-and-branches:
14 collab-\*
16 of new features to be introduced into the main branch when ready. Creating a new
17 collaboration branch requires a justification and TSC approval. Collaboration branches
18 shall be based off the main branch and any changes developed in the collab
19 branch shall target the main development branch. For released versions of
23 vx.y-branch
32 Changes submitted to a collaboration branch can evolve and improve
33 incrementally in a branch, before they are submitted to the mainline tree for
36 By dedicating an isolated branch to complex features, it's
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Drelease_process.rst6 The Zephyr project releases on a time-based cycle, rather than a feature-driven
10 A time-based release process enables the Zephyr project to provide users with a
12 roughly 4-month release cycle allows the project to coordinate development of
19 - Release tagging procedure:
21 - linear mode on main branch,
22 - release branches for maintenance after release tagging.
23 - Each release period will consist of a development phase followed by a
29 - Development phase: all changes are considered and merged, subject to
31 - Stabilisation phase: the release manager creates a vN-rc1 tag and the tree
33 - CI sees the tag, builds and runs tests; Test teams analyse the report from the
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Dlts.svg1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- Do not edit this file with editors other than diagrams.net -->
3 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
4-0.5 -0.5 711 192" content="&lt;mxfile host=&quot;app.diagrams.net&quot; modified=&quot;2022-03-29…
/Zephyr-latest/doc/services/device_mgmt/
Dmcumgr_backporting.rst15 The upstream MCUmgr repository is located `in this page <https://github.com/apache/mynewt-mcumgr>`_.
16 The Zephyr fork used in version 2.7 and earlier is `located here <https://github.com/zephyrproject-
17 …rary that is `part of the Zephyr code base <https://github.com/zephyrproject-rtos/zephyr/tree/main…
25 As such, there are four possible ways to apply a change to the 2.7 branch:
27 … done directly to the Zephyr held code of the MCUmgr library, is backported to the ``v2.7-branch``.
28 … ported to the Zephyr held code from the upstream repository, is backported to the ``v2.7-branch``.
30 to the ``v2.7-branch``.
32 directly applied to the ``v2.7-branch``.
56 You must also apply the ``backport v2.7-branch`` label to the bug report.
61 You can either create a *backport pull request* or a *new-fix pull request*.
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/Zephyr-latest/soc/renesas/rcar/rcar_gen3/r7/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
17 /* Invalidate instruction cache and flush branch target cache */ in soc_reset_hook()
/Zephyr-latest/doc/safety/
Dsafety_overview.rst9 This document is the safety documentation providing an overview over the safety-relevant activities
43 code base is pre-existing, we use the route 3s/1s approach defined by the IEC 61508 standard.
46 *Assessment of non-compliant development. Which is basically the route 1s with existing
57 electrical, electronic, and programmable electronic safety-related systems. Here's an overview of
74 safety-related system to ensure that it meets the specified SIL and other safety requirements.
79 documentation process to ensure that all aspects of the safety-related system are fully
84 implementation of safety-related systems that aims to reduce the risk of accidents and improve
85 overall safety. By following the standard, organizations can ensure that their safety-related
99 .. figure:: images/IEC-61508-basis.svg
102 :figclass: align-center
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/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/
DREADME.rst1 .. zephyr:code-sample:: eth-ivshmem
2 :name: Inter-VM Shared Memory (ivshmem) Ethernet
3 :relevant-api: ivshmem ethernet
17 Clone Jailhouse yocto project. At the time of writing, the "next" branch has
18 some fixes that are not yet on the "master" branch:
20 .. code-block:: console
22 git clone https://github.com/siemens/jailhouse-images.git
23 cd jailhouse-images
26 Open the menu, select "QEMU ARM64 virtual target" then "Save & Build"
29 .. code-block:: console
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/Zephyr-latest/doc/security/
Dsecurity-overview.rst1 .. _security-overview:
14 documents are created, this document is a top-level overview and entry
32 relevant sub-modules is created, threats are identified, and
39 Zephyr RTOS. This includes an evaluation target, its assets, and
43 .. figure:: media/security-process-steps.png
64 noted in RFC-2119, "These terms are frequently used to specify behavior
98 - **Security** **Functionality** with a focus on cryptographic
104 - **Quality Assurance** is driven by using a development process that
111 - **Execution Protection** including thread separation, stack and
164 - Verifying correct functionality of the implementation
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/Zephyr-latest/doc/develop/
Dmodules.rst7 order to avoid reinventing the wheel and to reuse as much well-established,
14 modules, an external project is required to have its own life-cycle outside
29 - Debugger integration
30 - Silicon vendor Hardware Abstraction Layers (HALs)
31 - Cryptography libraries
32 - File Systems
33 - Inter-Process Communication (IPC) libraries
36 references to optional :ref:`binary blobs <bin-blobs>`.
41 .. _modules-vs-projects:
47 <west-workspace>`. In fact, modules :ref:`do not require west
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/Zephyr-latest/.github/workflows/
Dcompliance.yml6 - edited
7 - opened
8 - reopened
9 - synchronize
13 runs-on: ubuntu-22.04
16 - name: Update PATH for west
20 - name: Checkout the code
24 fetch-depth: 0
26 - name: Rebase onto the target branch
30 git config --global user.email "you@example.com"
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Dtwister.yaml6 - main
7 - v*-branch
8 - collab-*
11 - main
12 - v*-branch
13 - collab-*
16 - cron: '0 3 * * 0'
19 group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
20 cancel-in-progress: true
23 twister-build-prep:
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/Zephyr-latest/boards/arduino/due/doc/
Dindex.rst11 SAM3X8E ARM Cortex-M3 CPU and the following devices:
37 +-----------+------------+----------------------+
40 | NVIC | on-chip | nested vectored |
42 +-----------+------------+----------------------+
43 | SYSTICK | on-chip | system clock |
44 +-----------+------------+----------------------+
45 | UART | on-chip | serial port |
46 +-----------+------------+----------------------+
47 | GPIO | on-chip | gpio |
48 +-----------+------------+----------------------+
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/Zephyr-latest/boards/lowrisc/opentitan_earlgrey/doc/
Dindex.rst9 The OpenTitan Earl Grey chip is a low-power secure microcontroller that is
17 - RV32IMCB RISC-V "Ibex" core
18 - 128kB main SRAM
19 - Fixed-frequency and AON timers
20 - 32 x GPIO
21 - 4 x UART
22 - 3 x I2C
23 - 2 x SPI host
24 - 1 x SPI device
25 - Various security peripherals
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/Zephyr-latest/boards/wiznet/w5500_evb_pico/doc/
Dindex.rst9 W5500-EVB-Pico is a microcontroller evaluation board based on the Raspberry
10 Pi RP2040 and fully hardwired TCP/IP controller W5500 - and basically works
13 drag-and-drop manner. It is also possible to flash and debug the boards with
18 - Dual core Arm Cortex-M0+ processor running up to 133MHz
19 - 264KB on-chip SRAM
20 - 16MB on-board QSPI flash with XIP capabilities
21 - 26 GPIO pins
22 - 3 Analog inputs
23 - 2 UART peripherals
24 - 2 SPI controllers
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/Zephyr-latest/doc/develop/test/
Dcoverage.rst11 * In a real embedded target or QEMU, using Zephyr's gcov integration
51 .. zephyr-app-commands::
53 :gen-args: -DCONFIG_COVERAGE=y -DCONFIG_COVERAGE_DUMP=y
58 the emulator with :kbd:`Ctrl-A X` for this to complete after the coverage dump
61 .. code-block:: console
63 ninja -Cbuild run | tee log.log
67 .. code-block:: console
69 ninja -Cbuild run | tee log.log
74 $ python3 scripts/gen_gcov_files.py -i log.log
80 $ find $ZEPHYR_SDK_INSTALL_DIR -iregex ".*gcov"
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/Zephyr-latest/boards/raspberrypi/rpi_pico/doc/
Dindex.rst6 The Raspberry Pi Pico and Pico W are small, low-cost, versatile boards from
7 Raspberry Pi. They are equipped with an RP2040 SoC, an on-board LED,
9 Infineon CYW43439 2.4 GHz Wi-Fi/Bluetooth module. The USB bootloader allows the
10 ability to flash without any adapter, in a drag-and-drop manner.
16 - Dual core Arm Cortex-M0+ processor running up to 133MHz
17 - 264KB on-chip SRAM
18 - 2MB on-board QSPI flash with XIP capabilities
19 - 26 GPIO pins
20 - 3 Analog inputs
21 - 2 UART peripherals
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/Zephyr-latest/scripts/west_commands/completion/
Dwest-completion.zsh4 # SPDX-License-Identifier: Apache-2.0
6 # Ensure this works also when being source-ed
9 typeset -A -g _opt_args
12 local -a builtin_cmds=(
25 local -a zephyr_ext_cmds=(
29 'sign[sign a Zephyr binary for bootloader chain-loading]'
34 'zephyr-export[export Zephyr installation as a CMake config package]'
40 local -a all_cmds=(${builtin_cmds} ${zephyr_ext_cmds})
42 if [[ -v WEST_COMP_CHECK_WORKSPACE ]]; then
44 if [ $? -eq 0 ]; then
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Dwest-completion.fish20 set -l tokens (commandline -opc)
41 set -l tokens (commandline -opc)
42 set -l argc (count $argv)
43 set -l max $argv[1]
44 set -l counter 0
46 if test $argc -eq 1
47 if test (math (count $tokens) - 2) -ge $max
60 if $counter -ge $max
77 set -l tokens (commandline -opc)
80 if string match -qr -- "$token*" "$tokens[-1]"
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/Zephyr-latest/arch/arc/core/
Dfault.c4 * SPDX-License-Identifier: Apache-2.0
66 if ((thread->base.user_options & K_USER) != 0) { in z_check_thread_stack_fail()
75 guard_end = thread->stack_info.start; in z_check_thread_stack_fail()
76 guard_start = (uint32_t)thread->stack_obj; in z_check_thread_stack_fail()
82 guard_end = thread->arch.priv_stack_start; in z_check_thread_stack_fail()
83 guard_start = guard_end - Z_ARC_STACK_GUARD_SIZE; in z_check_thread_stack_fail()
89 guard_end = thread->stack_info.start; in z_check_thread_stack_fail()
90 guard_start = guard_end - Z_ARC_STACK_GUARD_SIZE; in z_check_thread_stack_fail()
95 * (like enter_s {r13-r26, fp, blink}) push a collection of in z_check_thread_stack_fail()
113 * the technical manual, just switch on the values in Table 6-5
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/Zephyr-latest/doc/releases/
Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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Drelease-notes-1.7.rst10 nano- and micro-kernel APIs found in the 1.5.0 release and earlier.
52 * Added NXP FRDM-KW41Z board
53 * Added ST Nucleo-F334R8, Nucleo-L476G, STM3210C-EVAL, and STM32373C-EVAL boards
56 * Added Qemu target for RISC V and a simulator target for the Xtensa architecture.
102 * Created net-shell module for interacting with network sub-system.
136 * Imported Segger J-Link RTT library
145 * New local-content generation theme (read-the-docs)
147 * Site-wide glossary added.
150 * Improved consistency of :ref:`boards` and :zephyr:code-sample-category:`samples`.
159 * ``ZEP-19`` - IPSP node support
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Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
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/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.c4 * SPDX-License-Identifier: Apache-2.0
53 cfg = dev->config; in sai_mclk_config()
54 data = dev->data; in sai_mclk_config()
56 mclk_config.mclkOutputEnable = cfg->mclk_is_output; in sai_mclk_config()
65 ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate); in sai_mclk_config()
73 LOG_DBG("target MCLK is %u", bespoke->mclk_rate); in sai_mclk_config()
78 /* target MCLK rate */ in sai_mclk_config()
79 mclk_config.mclkHz = bespoke->mclk_rate; in sai_mclk_config()
82 SAI_SetMasterClockConfig(UINT_TO_I2S(data->regmap), &mclk_config); in sai_mclk_config()
84 set_msel(data->regmap, msel); in sai_mclk_config()
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/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem.c5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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/Zephyr-latest/arch/arm64/core/
Dfatal.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Kernel fatal error handler for ARM64 Cortex-A
11 * This module provides the z_arm64_fatal_error() routine for ARM64 Cortex-A
12 * CPUs and z_arm64_do_kernel_oops() routine to manage software-generated fatal
38 cpu_id = arch_curr_cpu()->id; in z_arm64_safe_exception_stack_init()
41 arch_curr_cpu()->arch.safe_exception_stack = (uint64_t)safe_exc_sp; in z_arm64_safe_exception_stack_init()
44 arch_curr_cpu()->arch.current_stack_limit = 0UL; in z_arm64_safe_exception_stack_init()
45 arch_curr_cpu()->arch.corrupted_sp = 0UL; in z_arm64_safe_exception_stack_init()
85 "floating-point functionality"; in dump_esr()
91 err = "Branch Target Exception"; in dump_esr()
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