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/Zephyr-latest/boards/digilent/arty_a7/support/
Dopenocd_arty_a7_arm_designstart_m1.cfg1 source [find interface/cmsis-dap.cfg]
2 source [find target/swj-dp.tcl]
11 source [find openocd_arty_a7_arm_designstart.cfg]
Dopenocd_arty_a7_arm_designstart_m3.cfg1 source [find interface/cmsis-dap.cfg]
2 source [find target/swj-dp.tcl]
11 source [find openocd_arty_a7_arm_designstart.cfg]
/Zephyr-latest/dts/bindings/pinctrl/
Dst,stm32f1-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
27 - "disable"
[all …]
/Zephyr-latest/boards/sc/scobc_module1/support/
Dopenocd.cfg1 source [find interface/cmsis-dap.cfg]
3 source [find target/swj-dp.tcl]
12 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
13 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
16 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
17 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
/Zephyr-latest/boards/arm/v2m_beetle/support/
Dopenocd.cfg1 # Config Beetle SoC providing a CMSIS-DAP interface.
3 source [find interface/cmsis-dap.cfg]
5 source [find target/swj-dp.tcl]
29 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
31 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
33 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x1000 -work-area-backup 0
/Zephyr-latest/boards/ene/kb1200_evb/support/
Dopenocd.cfg1 # SPDX-License-Identifier: GPL-2.0-or-later
3 source [find interface/jlink.cfg]
7 source [find target/swj-dp.tcl]
17 # SWD DAP ID of ENE KB1200 Cortex-M4.
24 # Work-area is a space in RAM used for flash programming
33 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
34 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
36 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
38 $_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
46 $_TARGETNAME configure -event reset-start {adapter speed 600}
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_stm32.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
6 * SPDX-License-Identifier: Apache-2.0
121 /* ignore swj-cfg reset state (default value) */
130 /* reset state is '000' (Full SWJ, (JTAG-DP + SW-DP)) */ in stm32f1_swj_cfg_init()
133 /* 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST */ in stm32f1_swj_cfg_init()
137 /* 010: JTAG-DP Disabled and SW-DP Enabled */ in stm32f1_swj_cfg_init()
141 /* 100: JTAG-DP Disabled and SW-DP Disabled */ in stm32f1_swj_cfg_init()
164 * @retval -EINVAL If pins have an incompatible set of remaps.
180 return -EINVAL; in stm32_pins_remap()
189 /* read initial value, ignore write-only SWJ_CFG */ in stm32_pins_remap()
[all …]
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5.dtsi7 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/adc/adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/clock/stm32u5_clock.h>
15 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #include <zephyr/dt-bindings/flash_controller/ospi.h>
18 #include <zephyr/dt-bindings/reset/stm32u5_reset.h>
19 #include <zephyr/dt-bindings/dma/stm32_dma.h>
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-2.0.rst12 * The kernel now supports both 32- and 64-bit architectures.
17 * We added support for :ref:`Point-to-Point Protocol (PPP) <ppp>`. PPP is a
20 * We added support for UpdateHub, an end-to-end solution for large scale
21 over-the-air device updates.
22 * We added support for ARM Cortex-R Architecture (Experimental).
32 * Fixes CVE-2019-9506: The Bluetooth BR/EDR specification up to and
35 negotiation. This allows practical brute-force attacks (aka "KNOB")
42 * New kernel API for per-thread disabling of Floating Point Services for
43 ARC, ARM Cortex-M, and x86 architectures.
45 * Additional support for compatibility with 64-bit architectures.
[all …]
Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
89 * STM32F1 Serial wire JTAG configuration (SWJ CFG) configuration choice
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
[all …]