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/Zephyr-Core-3.5.0/drivers/spi/
DKconfig.stm321 # STM32 SPI driver configuration options
3 # Copyright (c) 2015-2016 Intel Corporation
4 # SPDX-License-Identifier: Apache-2.0
7 bool "STM32 MCU SPI controller driver"
12 Enable SPI support on the STM32 family of processors.
17 bool "STM32 MCU SPI Interrupt Support"
19 Enable Interrupt support for the SPI Driver of STM32 family.
22 bool "STM32 MCU SPI DMA Support"
26 Enable the SPI DMA mode for SPI instances
30 bool "STM32 Hardware Slave Select support"
/Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/
Dtestcase.yaml2 depends_on: spi
4 - drivers
5 - spi
6 - dma
7 filter: dt_compat_enabled("test-spi-loopback-slow") and
8 dt_compat_enabled("test-spi-loopback-fast")
13 drivers.spi.loopback: {}
14 drivers.spi.loopback.internal:
16 drivers.spi.loopback.lpspi.dma:
19 - CONFIG_SPI_MCUX_LPSPI_DMA=y
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/mp1/
Dstm32mp157.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_clock.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
18 #include <zephyr/dt-bindings/display/panel.h>
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/h5/
Dstm32h562.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
14 #clock-cells = <0>;
15 compatible = "st,stm32u5-pll-clock";
21 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
23 pinctrl: pin-controller@42020000 {
25 compatible = "st,stm32-gpio";
26 gpio-controller;
27 #gpio-cells = <2>;
33 compatible = "st,stm32-gpio";
[all …]
/Zephyr-Core-3.5.0/dts/bindings/spi/
Dst,stm32-spi.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 SPI controller
6 compatible: "st,stm32-spi"
8 include: st,stm32-spi-common.yaml
Dst,stm32-spi-fifo.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 SPI controller with embedded Rx and Tx FIFOs
6 compatible: "st,stm32-spi-fifo"
8 include: st,stm32-spi-common.yaml
Dst,stm32-spi-host-cmd.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Host Command version of STM32 SPI controller.
8 compatible: "st,stm32-spi-host-cmd"
10 include: st,stm32-spi.yaml
Dst,stm32-spi-subghz.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 SUBGHZ SPI controller
6 compatible: "st,stm32-spi-subghz"
9 - name: st,stm32-spi-common.yaml
10 property-blocklist:
11 - pinctrl-0
12 - pinctrl-names
15 use-subghzspi-nss:
Dst,stm32h7-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32H7 SPI controller
6 This compatible stands for all SPI hardware blocks matching the
8 This version of STM32 SPI hardware block could be identified by the
12 compatible: "st,stm32h7-spi"
14 include: st,stm32-spi-common.yaml
/Zephyr-Core-3.5.0/dts/arm/st/l4/
Dstm32l431.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l431", "st,stm32l4", "simple-bus";
14 clk_hsi48: clk-hsi48 {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <DT_FREQ_M(48)>;
22 pinctrl: pin-controller@48000000 {
25 compatible = "st,stm32-gpio";
28 gpio-controller;
29 #gpio-cells = <2>;
[all …]
Dstm32l451.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l451", "st,stm32l4", "simple-bus";
14 clk_hsi48: clk-hsi48 {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <DT_FREQ_M(48)>;
22 pinctrl: pin-controller@48000000 {
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
[all …]
Dstm32l471.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l471", "st,stm32l4", "simple-bus";
13 pinctrl: pin-controller@48000000 {
16 compatible = "st,stm32-gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
32 compatible = "st,stm32-gpio";
[all …]
Dstm32l433.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l433", "st,stm32l4", "simple-bus";
13 pinctrl: pin-controller@48000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
23 compatible = "st,stm32-gpio";
24 gpio-controller;
25 #gpio-cells = <2>;
32 compatible = "st,stm32-i2c-v2";
[all …]
/Zephyr-Core-3.5.0/doc/services/device_mgmt/
Dec_host_cmd.rst39 Another case is SPI. Unfortunately, the current SPI API can't be used to handle the host commands
40 communication. The main issues are unknown command size sent by the host (the SPI transaction
41 sends/receives specific number of bytes) and need to constant sending status byte (the SPI module
42 is enabled and disabled per transaction). It forces implementing the SPI driver within a backend,
43 as it is done for SHI. That means a SPI backend has to be implemented per chip family. However, it
44 can be changed in the future once the SPI API is extended to host command needs. Please check `the
45 discussion <https://github.com/zephyrproject-rtos/zephyr/issues/56091>`_.
47 That approach requires configuring the SPI dts node in a special way. The main compatible string of
48 a SPI node has changed to use the Host Command version of a SPI driver. The rest of the properties
49 should be configured as usual. Example of the SPI node for STM32:
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/f4/
Dstm32f427.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/stm32f427_clock.h>
9 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
13 compatible = "st,stm32f427", "st,stm32f4", "simple-bus";
15 pinctrl: pin-controller@40020000 {
19 compatible = "st,stm32-gpio";
20 gpio-controller;
21 #gpio-cells = <2>;
27 compatible = "st,stm32-gpio";
28 gpio-controller;
[all …]
Dstm32f401.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #clock-cells = <0>;
13 compatible = "st,stm32f4-plli2s-clock";
19 compatible = "st,stm32f401", "st,stm32f4", "simple-bus";
21 spi2: spi@40003800 {
22 compatible = "st,stm32-spi";
23 #address-cells = <1>;
24 #size-cells = <0>;
31 spi3: spi@40003c00 {
32 compatible = "st,stm32-spi";
[all …]
Dstm32f410.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
16 compatible = "st,stm32f410", "st,stm32f4", "simple-bus";
18 spi2: spi@40003800 {
19 compatible = "st,stm32-spi";
20 #address-cells = <1>;
21 #size-cells = <0>;
28 spi5: spi@40015000 {
29 compatible = "st,stm32-spi";
30 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/f3/
Dstm32f302.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
12 compatible = "st,stm32f302", "st,stm32f3", "simple-bus";
20 compatible = "st,stm32-i2c-v2";
21 clock-frequency = <I2C_BITRATE_STANDARD>;
22 #address-cells = <1>;
23 #size-cells = <0>;
31 interrupt-names = "event", "error";
36 compatible = "st,stm32-i2c-v2";
37 clock-frequency = <I2C_BITRATE_STANDARD>;
[all …]
Dstm32f373.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32f1_adc.h>
12 compatible = "st,stm32f373", "st,stm32f3", "simple-bus";
19 compatible = "st,stm32f1-rcc";
22 pinctrl: pin-controller@48000000 {
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
33 compatible = "st,stm32-i2c-v2";
34 clock-frequency = <I2C_BITRATE_STANDARD>;
[all …]
Dstm32f303.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
12 compatible = "st,stm32f303", "st,stm32f3", "simple-bus";
20 compatible = "st,stm32-i2c-v2";
21 clock-frequency = <I2C_BITRATE_STANDARD>;
22 #address-cells = <1>;
23 #size-cells = <0>;
31 interrupt-names = "event", "error";
35 spi2: spi@40003800 {
[all …]
/Zephyr-Core-3.5.0/samples/drivers/spi_flash/
Dsample.yaml2 name: SPI Flash Sample
4 sample.drivers.spi.flash:
6 - spi
7 - flash
8 filter: dt_compat_enabled("jedec,spi-nor") or dt_compat_enabled("st,stm32-qspi-nor")
9 or dt_compat_enabled("st,stm32-ospi-nor")
16 - "Test 1: Flash erase"
17 - "Flash erase succeeded!"
18 - "Test 2: Flash write"
19 - "Attempting to write 4 bytes"
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h7.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/f0/
Dstm32f051.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32f051", "st,stm32f0", "simple-bus";
14 compatible = "st,stm32-usart", "st,stm32-uart";
23 compatible = "st,stm32-i2c-v2";
24 clock-frequency = <I2C_BITRATE_STANDARD>;
25 #address-cells = <1>;
26 #size-cells = <0>;
30 interrupt-names = "combined";
34 spi2: spi@40003800 {
35 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
[all …]
Dstm32f042.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32f042", "st,stm32f0", "simple-bus";
14 clk_hsi48: clk-hsi48 {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <DT_FREQ_M(48)>;
23 compatible = "st,stm32-usart", "st,stm32-uart";
31 spi2: spi@40003800 {
32 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
33 #address-cells = <1>;
[all …]
Dstm32f030X8.dtsi4 * SPDX-License-Identifier: Apache-2.0
15 flash-controller@40022000 {
22 compatible = "st,stm32-usart", "st,stm32-uart";
31 compatible = "st,stm32-i2c-v2";
32 clock-frequency = <I2C_BITRATE_STANDARD>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 interrupt-names = "combined";
42 spi2: spi@40003800 {
43 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
[all …]

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