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/sof-2.7.6/tools/tune/multiband_drc/
Diir_gen_quant_coefs.m9 % Generate the coefficients of (de)emphasis for the 1-st stage of biquads
15 % Generate the coefficients of (de)emphasis for the 2-nd stage of biquads
19 % Adjust the stage gain (push gains to the last stage) of emphasis filter
46 % will do the stage gain adjustment afterwards.
114 rshift--; % left-shift in shift stage
Dexample_multiband_drc.m21 % stage_gain: The gain of each emphasis filter stage
23 % stage_ratio: The frequency ratio for each emphasis filter stage to the
24 % previous stage
/sof-2.7.6/installer/
DREADME.md32 To stage and install in one go:
34 make -C installer/ stage rsync
36 "stage" is the default target and it tries to stage everything:
41 You can use `make -jN stage` to build multiple platforms faster but do
42 *not* `make -jN stage rsync` as this will start deploying before the
DGNUmakefile6 .DEFAULT_GOAL := stage
7 .PHONY: clean stage rsync
72 stage: signed unsigned ldicts aliases topologies target
119 ### Stage sof-*.ri firmware files and symbolic links ####
173 ### Stage *.ldc logger dictionaries ###
223 ### Stage sof-tplg/ topologies ###
272 compare: stage
/sof-2.7.6/
D.travis.yml19 # only as presentation labels. Nothing in stage "tests" will run if
31 # stage buildonly
34 stage: buildonly
55 # stage tests
58 stage: tests
/sof-2.7.6/tools/tune/src/
Dsrc_generate.m114 % When decimating 1st stage passband can be limited
120 % When interpolating 2nd stage passband can be limited
127 % Allow half ripple for dual stage SRC parts
168 %% Print 2 stage conversion factors
172 fprintf(fh,'Dual stage fractional SRC: Ratios\n');
188 %% Print 2 stage MOPS
189 fprintf(fh,'Dual stage fractional SRC: MOPS\n');
210 %% Print 2 stage MOPS per stage
211 fprintf(fh,'Dual stage fractional SRC: MOPS per stage\n');
Dsrc_factor2_lm.m71 l01 = 4; m01 = 3; l02 = l/l01; m02 = m/m01; % 24 to 32, no 2 stage
74 l01 = 3; m01 = 4; l02 = l/l01; m02 = m/m01; % 24 to 32, no 2 stage
119 %% If 1st stage is 1:1
/sof-2.7.6/.github/workflows/
Dinstaller.yml32 - name: build all and stage
33 run: ./scripts/docker-run.sh make -j3 -C installer/ stage
/sof-2.7.6/src/audio/src/
Dsrc.c164 /* Stage 1 is repeated max. amount that just exceeds one in src_buffer_lengths()
169 /* Set sbuf length to allow storing two stage 1 output in src_buffer_lengths()
172 * variable number of blocks to process per each stage in src_buffer_lengths()
276 /* Get setup for 2 stage conversion */ in src_polyphase_init()
284 * stage length is one if conversion needs only one stage. in src_polyphase_init()
286 * use a simple copy function instead of 1 stage FIR with one in src_polyphase_init()
293 /* If filter length for first stage is zero this is a deleted in src_polyphase_init()
312 /* Normal 2 stage SRC */
340 s1.stage = cd->src.stage1; in src_2s()
352 s2.stage = cd->src.stage2; in src_2s()
[all …]
Dsrc_generic.c238 struct src_stage *cfg = s->stage; in src_polyphase_stage_cir()
339 struct src_stage *cfg = s->stage; in src_polyphase_stage_cir_s16()
Dsrc_hifi2ep.c315 struct src_stage *cfg = s->stage; in src_polyphase_stage_cir()
441 struct src_stage *cfg = s->stage; in src_polyphase_stage_cir_s16()
Dsrc_hifi3.c319 struct src_stage *cfg = s->stage; in src_polyphase_stage_cir()
446 struct src_stage *cfg = s->stage; in src_polyphase_stage_cir_s16()
/sof-2.7.6/src/include/ipc/
Ddai.h57 #define SOF_DAI_CONFIG_FLAGS_NONE (0 << 0) /**< DAI_CONFIG sent without stage information */
58 #define SOF_DAI_CONFIG_FLAGS_HW_PARAMS (1 << 0) /**< DAI_CONFIG sent during hw_params stage */
59 #define SOF_DAI_CONFIG_FLAGS_HW_FREE (2 << 0) /**< DAI_CONFIG sent during hw_free stage */
/sof-2.7.6/src/arch/xtensa/xtos/xea1/
Dexc-alloca-handler.S109 // (12 cycles from vector to here, assuming cache hits, 5-stage pipe, etc)
156 // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, no zoloops, etc)
257 // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc)
265 // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc)
Dwindow-vectors.S88 // Instruction+bubbles Totals (5-stage)
97 // Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
98 // Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
/sof-2.7.6/src/include/sof/audio/src/
Dsrc.h73 struct src_stage *stage; member
/sof-2.7.6/src/arch/xtensa/xtos/xea2/
Dwindow-vectors.S87 // Instruction+bubbles Totals (5-stage)
96 // Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
97 // Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
/sof-2.7.6/src/include/sof/lib/
Dperf_cnt.h88 * For simple performance measurement and optimization in development stage,
/sof-2.7.6/src/include/sof/schedule/
Dll_schedule_domain.h48 uint64_t new_target_tick; /**< for the next set, used during the reschedule stage */
/sof-2.7.6/src/drivers/intel/ssp/
Dssp.c725 dai_info(dai, "ssp_set_config(): hw_params stage: enabled MCLK clocks for SSP%d...", in ssp_set_config_tplg()
754 dai_info(dai, "ssp_set_config(): hw_params stage: enabled BCLK clocks for SSP%d...", in ssp_set_config_tplg()
760 dai_info(dai, "ssp_set_config(): hw_free stage: releasing BCLK clocks for SSP%d...", in ssp_set_config_tplg()
775 dai_info(dai, "ssp_set_config: hw_free stage: releasing MCLK clocks for SSP%d...", in ssp_set_config_tplg()
/sof-2.7.6/src/arch/xtensa/xtos/
Dxtos-internal.h164 // T10xx (Athens) and Xtensa LX microarchitectures (both 5 and 7 stage pipes):
197 // Xtensa LX microarchitectures with 7-stage pipe; otherwise only two
/sof-2.7.6/tools/probes/
Dprobes_main.c46 READY = 0, /**< At this stage app is looking for a SYNC word */
/sof-2.7.6/src/include/sof/audio/codec_adapter/codec/
Dgeneric.h118 * reset in .reset(). This should reset all parameters to their initial stage
/sof-2.7.6/src/platform/amd/renoir/include/arch/xtensa/config/
Dcore-isa.h167 (1 = 5-stage, 2 = 7-stage) */
/sof-2.7.6/src/audio/
Dcomponent.c297 * 1. At first boot and topology parsing stage, the driver will in comp_data_blob_set_cmd()

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