Searched full:spi1 (Results 1 – 25 of 410) sorted by relevance
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| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/ |
| D | test_stm32_clock_configuration.c | 38 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); in ZTEST()
49 zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on"); in ZTEST()
50 TC_PRINT("SPI1 gating clock on\n"); in ZTEST()
52 if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { in ZTEST()
58 TC_PRINT("SPI1 domain clk configured\n"); in ZTEST()
105 zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be off"); in ZTEST()
106 TC_PRINT("SPI1 gating clock off\n"); in ZTEST()
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| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/ |
| D | test_stm32_clock_configuration.c | 38 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); in ZTEST()
50 zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on"); in ZTEST()
51 TC_PRINT("SPI1 reg_clk on\n"); in ZTEST()
53 if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { in ZTEST()
61 TC_PRINT("SPI1 domain_clk on\n"); in ZTEST()
136 TC_PRINT("SPI1 clock freq: %d MHz\n", spi1_actual_clk_freq / (1000*1000)); in ZTEST()
143 zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be off"); in ZTEST()
144 TC_PRINT("SPI1 reg_clk off\n"); in ZTEST()
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| /Zephyr-Core-3.5.0/boards/shields/buydisplay_2_8_tft_touch_arduino/boards/ |
| D | nrf52840dk_nrf52840.overlay | 7 /* NOTE: spi1 MISO pin is used by the display for the cmd/data line */
8 &spi1 {
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| /Zephyr-Core-3.5.0/boards/shields/buydisplay_3_5_tft_touch_arduino/boards/ |
| D | nrf52840dk_nrf52840.overlay | 7 /* NOTE: spi1 MISO pin is used by the display for the cmd/data line */
8 &spi1 {
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| /Zephyr-Core-3.5.0/boards/arm/bbc_microbit/ |
| D | board.h | 28 #define EXT_P13_GPIO_PIN 23 /* P13, SPI1 SCK */
29 #define EXT_P14_GPIO_PIN 22 /* P14, SPI1 MISO */
30 #define EXT_P15_GPIO_PIN 21 /* P15, SPI1 MOSI */
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| /Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/ |
| D | nucleo_f207zg.overlay | 7 &spi1 {
13 &spi1 {
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| D | nucleo_f411re.overlay | 7 &spi1 {
13 &spi1 {
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| D | nucleo_f429zi.overlay | 7 &spi1 {
13 &spi1 {
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| D | nucleo_h723zg.overlay | 13 /* Define PLL1_Q as SPI1 kernel clock source */
14 &spi1 {
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| D | adp_xc7k_ae350.overlay | 7 &spi1 {
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| D | stm32f3_disco.overlay | 7 &spi1 {
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| D | emsdp.overlay | 7 &spi1 {
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| /Zephyr-Core-3.5.0/boards/arm/particle_argon/dts/ |
| D | mesh_feather_spi_spi1.dtsi | 7 /* Add SPI support on Particle Mesh via nRF52840 SPI1
31 feather_spi: &spi1 { /* feather SPI */
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| /Zephyr-Core-3.5.0/boards/arm/particle_xenon/dts/ |
| D | mesh_feather_spi_spi1.dtsi | 7 /* Add SPI support on Particle Mesh via nRF52840 SPI1
31 feather_spi: &spi1 { /* feather SPI */
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| /Zephyr-Core-3.5.0/include/zephyr/devicetree/ |
| D | spi.h | 34 * spi1: spi@... {
46 * DT_SPI_HAS_CS_GPIOS(DT_NODELABEL(spi1)) // 1
59 * spi1: spi@... {
71 * DT_SPI_NUM_CS_GPIOS(DT_NODELABEL(spi1)) // 2
86 * spi1: spi@... {
169 * spi1: spi@... {
202 * spi1: spi@... {
232 * spi1: spi@... {
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| /Zephyr-Core-3.5.0/samples/drivers/led_apa102/boards/ |
| D | nucleo_l432kc.overlay | 7 &spi1 {
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| /Zephyr-Core-3.5.0/boards/arm/nucleo_l073rz/ |
| D | nucleo_l073rz.dts | 44 /* NOTE: disabled by default, PWM2 conflicts with SPI1 */
125 &spi1 {
158 /* NOTE: disabled by default, PWM2 conflicts with SPI1 */
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| /Zephyr-Core-3.5.0/boards/arm/arduino_nicla_sense_me/ |
| D | arduino_nicla_sense_me.dts | 81 /* Cannot be used together with spi1. */
88 /* SPI1 in datasheet */
89 &spi1 {
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| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/ |
| D | spi1_pclk2.overlay | 12 &spi1 {
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| D | spi1_sysclk.overlay | 12 &spi1 {
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| D | spi1_hsi_16.overlay | 16 &spi1 {
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| D | spi1_msik.overlay | 18 &spi1 {
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| /Zephyr-Core-3.5.0/dts/arm/cypress/ |
| D | psoc6-pinctrl.dtsi | 19 DT_CYPRESS_HSIOM(spi1, mosi, 10, 0, act_8, drive-push-pull);
20 DT_CYPRESS_HSIOM(spi1, miso, 10, 1, act_8, input-enable);
21 DT_CYPRESS_HSIOM(spi1, clk, 10, 2, act_8, drive-push-pull);
22 DT_CYPRESS_HSIOM(spi1, sel0, 10, 3, act_8, drive-push-pull);
23 DT_CYPRESS_HSIOM(spi1, sel1, 10, 4, act_8, drive-push-pull);
24 DT_CYPRESS_HSIOM(spi1, sel2, 10, 5, act_8, drive-push-pull);
25 DT_CYPRESS_HSIOM(spi1, sel3, 10, 6, act_8, drive-push-pull);
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| /Zephyr-Core-3.5.0/samples/boards/nrf/nrfx_prs/boards/ |
| D | nrf9160dk_nrf9160.overlay | 44 &spi1 {
84 * to the spi1 node (17, 18, and 19).
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| /Zephyr-Core-3.5.0/samples/subsys/fs/fs_sample/boards/ |
| D | nrf52840_blip.overlay | 7 &spi1 {
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