Searched full:spi0 (Results 1 – 25 of 224) sorted by relevance
123456789
| /Zephyr-Core-3.6.0/dts/bindings/spi/ |
| D | sifive,spi0.yaml | 7 Note: First instance of the Sifive SPI controller (spi0) must be kept
11 compatible: "sifive,spi0"
|
| /Zephyr-Core-3.6.0/boards/arm/sam_v71_xult/ |
| D | sam_v71_xult-common.dtsi | 90 <12 0 &piod 25 0>, /* SPI0(NPCS1) */
91 <13 0 &piod 21 0>, /* SPI0(MOSI) EXT2 */
92 <14 0 &piod 20 0>, /* SPI0(MISO) EXT2 */
93 <15 0 &piod 22 0>; /* SPI0(SCK) EXT2 */
115 <12 0 &piod 27 0>, /* SPI0(NPCS3) */
116 <13 0 &piod 21 0>, /* SPI0(MOSI) EXT1 */
117 <14 0 &piod 20 0>, /* SPI0(MISO) EXT1 */
118 <15 0 &piod 22 0>; /* SPI0(SCK) EXT1 */
194 &spi0 {
342 ext1_spi: &spi0 {
[all …]
|
| /Zephyr-Core-3.6.0/tests/drivers/spi/spi_loopback/boards/ |
| D | ucans32k1sic.overlay | 7 /* Short P1.3 (SPI0/MISO) with P1.4 (SPI0/MOSI) */
|
| D | rpi_pico_delete_dma_props.overlay | 7 &spi0 {
|
| D | tdk_robokit1.overlay | 7 &spi0 {
|
| D | cc1352r1_launchxl.overlay | 7 &spi0 {
|
| D | frdm_k64f.overlay | 7 &spi0 {
|
| D | frdm_kw41z.overlay | 7 &spi0 {
|
| D | em_starterkit.overlay | 7 &spi0 {
|
| D | intel_adl_crb.overlay | 9 &spi0 {
|
| D | intel_rpl_p_crb.overlay | 9 &spi0 {
|
| /Zephyr-Core-3.6.0/samples/drivers/spi_flash/boards/ |
| D | em_starterkit.overlay | 7 &spi0 {
|
| /Zephyr-Core-3.6.0/tests/drivers/flash/common/boards/ |
| D | nrf52840dk_spi_nor.overlay | 36 &spi0 {
48 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
|
| D | nrf52840dk_spi_nor_wp_hold.overlay | 36 &spi0 {
48 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
|
| /Zephyr-Core-3.6.0/dts/riscv/sifive/ |
| D | riscv64-fu540.dtsi | 146 spi0: spi@10040000 { label
147 compatible = "sifive,spi0";
158 compatible = "sifive,spi0";
169 compatible = "sifive,spi0";
|
| D | riscv64-fu740.dtsi | 168 spi0: spi@10040000 { label
169 compatible = "sifive,spi0";
180 compatible = "sifive,spi0";
191 compatible = "sifive,spi0";
|
| /Zephyr-Core-3.6.0/tests/drivers/sensor/icm42688/boards/ |
| D | native_sim.overlay | 5 &spi0 {
|
| /Zephyr-Core-3.6.0/tests/boards/mec172xevb_assy6906/qspi/boards/ |
| D | mec172xevb_assy6906.overlay | 7 &spi0 {
|
| /Zephyr-Core-3.6.0/samples/sensor/bme280/boards/ |
| D | rpi_pico.overlay | 1 &spi0 {
|
| /Zephyr-Core-3.6.0/tests/boards/mec15xxevb_assy6853/qspi/boards/ |
| D | mec15xxevb_assy6853.overlay | 7 &spi0 {
|
| /Zephyr-Core-3.6.0/dts/bindings/dma/ |
| D | gd,gd32-dma.yaml | 48 &spi0 {
58 "spi0" uses dma0 for transmitting and receiving in the example.
|
| /Zephyr-Core-3.6.0/tests/drivers/spi/spi_loopback/ |
| D | overlay-mcux-dspi-dma.overlay | 7 &spi0 {
|
| /Zephyr-Core-3.6.0/tests/drivers/sensor/bmi160/boards/ |
| D | native_sim.overlay | 12 &spi0 {
|
| /Zephyr-Core-3.6.0/samples/drivers/espi/boards/ |
| D | mec15xxevb_assy6853.overlay | 21 &spi0 {
|
| /Zephyr-Core-3.6.0/boards/arc/emsdp/ |
| D | platform.c | 14 /* Enable clock for DFSS SPI0 controller & DFSS SPI1 controller */
|
123456789
