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/Zephyr-Core-3.5.0/dts/bindings/memory-controllers/
Dst,stm32-fmc-sdram.yaml153 the same TXSR timing corresponding to the slowest SDRAM device
158 used, the TRC must be programmed with the timings of the slowest
164 programmed with the timing of the slowest device in both banks.
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dnxp,s32k3-pinctrl.yaml99 - "slowest"
102 Slew rate control. Can be either slowest or fastest setting.
/Zephyr-Core-3.5.0/tests/bsim/bluetooth/mesh/src/
Dtest_sar.c306 "Send a 32-segment message with SAR configured with slowest timings."),
308 "Receive a 32-segment message with with SAR configured with slowest timings."),
/Zephyr-Core-3.5.0/drivers/sensor/lis2mdl/
Dlis2mdl.c25 * signal. The slowest value we could measure by I2C frequency of 100000HZ was
/Zephyr-Core-3.5.0/drivers/sensor/lsm6dso/
Dlsm6dso_shub.c406 int tries = 200; /* Should be max ~160 ms, from 2 cycles at slowest ODR 12.5 Hz */ in lsm6dso_shub_wait_completed()
/Zephyr-Core-3.5.0/drivers/sensor/lsm6dso16is/
Dlsm6dso16is_shub.c501 int tries = 200; /* Should be max ~160 ms, from 2 cycles at slowest ODR 12.5 Hz */ in lsm6dso16is_shub_wait_completed()
/Zephyr-Core-3.5.0/drivers/sensor/lsm6dsv16x/
Dlsm6dsv16x_shub.c501 int tries = 200; /* Should be max ~160 ms, from 2 cycles at slowest ODR 12.5 Hz */ in lsm6dsv16x_shub_wait_completed()
/Zephyr-Core-3.5.0/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_spi_stm32.c83 * This affects the slowest SPI clock we can support. A delay of 8192 us
Dec_host_cmd_backend_shi_npcx.c42 * This affects the slowest SPI clock we can support. A delay of 8192 us permits a 512-byte request
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_cadence_qspi_nor_ll.c502 /*1. Set divider to bigger value (slowest SCLK) in cad_qspi_calibration()
Dflash_stm32_qspi.c1059 /* query supported read modes, begin from the slowest */ in spi_nor_process_bfp()
Dflash_stm32_ospi.c1792 /* determine supported read modes, begin from the slowest */ in spi_nor_process_bfp()