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/hal_gigadevice-latest/pinconfigs/
DREADME.md4 multiple GD32 devices, for example, that `USART0_TX` signal can only be mapped
8 GD32 devices use two distinct models to configure signal multiplexing. In
28 - `model` (required): Choose between `afio` or `af`
29 - `series` (required): Series name, e.g. gd32vf103
30 - `variants` (required): Each variant has a different set of valid pin
42 - pincode: V
44 - pincode: R
47 # less peripherals (and so less signals) than B-8.
48 - pincode: R
56 - `signal-configs` (required): A dictionary of signal configurations. Each
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Dgd32f350xx.yml4 # - GD32F350XX Datasheet (Revision 1.5)
8 # - 28 pins: G
9 # - 32 pins: K
10 # - 48 pins: C
11 # - 64 pins: R
15 # - 16Kb Flash, 4Kb SRAM: 4
16 # - 32Kb Flash, 6Kb SRAM: 6
17 # - 64Kb Flash, 8Kb SRAM: 8
18 # - 64Kb Flash, 16Kb SRAM: 8(GD32F350R8 only)
19 # - 128Kb Flash, 16Kb SRAM: B
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Dgd32l233xx.yml5 # - GD32L233XX Datasheet (Revision 1.2)
9 # - 32 pins: Q (GD32L233Kx-QFN32)
10 # - 32 pins: K (GD32L233Kx-LQFP32)
11 # - 48 pins: C
12 # - 64 pins: R
16 # - 64Kb Flash, 16Kb SRAM: 8
17 # - 128Kb Flash, 24Kb SRAM: B
18 # - 256Kb Flash, 32Kb SRAM: C
21 # SPDX-License-Identifier: Apache 2.0
28 - pincode: Q
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Dgd32vf103xx.yml4 # - GD32VF103XX Datasheet (Revision 1.2)
5 # - GD32VF103 User Manual (Revision 1.2)
9 # - 100 pins: V
10 # - 64 pins: R
11 # - 48 pins: C
12 # - 36 pins: T
16 # - 128Kb Flash, 32Kb SRAM: B
17 # - 64Kb Flash, 20Kb SRAM: 8
18 # - 32Kb Flash, 10Kb SRAM: 6
19 # - 16Kb Flash, 6Kb SRAM: 4
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Dgd32e103xx.yml4 # - GD32E103XX Datasheet (Revision 1.5)
5 # - GD32E103 User Manual (Revision 1.5)
9 # - 100 pins: V
10 # - 64 pins: R
11 # - 48 pins: C
12 # - 36 pins: T
16 # - 128Kb Flash, 32Kb SRAM: B
17 # - 64Kb Flash, 20Kb SRAM: 8
20 # SPDX-License-Identifier: Apache 2.0
27 - pincode: V
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Dgd32f403xx.yml4 # - GD32F403XX Datasheet (Revision 1.2)
5 # - GD32F403 User Manual (Revision 2.1)
9 # - 144 pins: Z
10 # - 100 pins: V
11 # - 64 pins: R
15 # - 3072Kb Flash, 128Kb SRAM: K
16 # - 2048Kb Flash, 128Kb SRAM: I
17 # - 1024Kb Flash, 128Kb SRAM: G
18 # - 512Kb Flash, 96Kb SRAM: E
19 # - 256Kb Flash, 64Kb SRAM: C
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Dgd32e507xx.yml4 # - GD32E507XX Datasheet (Revision 1.4)
5 # - GD32E50X User Manual (Revision 1.0)
9 # - 144 pins: Z
10 # - 100 pins: V
11 # - 64 pins: R
15 # - 512Kb Flash, 128Kb SRAM: E
16 # - 256Kb Flash, 96Kb SRAM: C
19 # SPDX-License-Identifier: Apache 2.0
26 - pincode: Z
28 - pincode: V
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/hal_gigadevice-latest/scripts/
Dgd32pinctrl.py5 python3 gd32pinctrl.py [-i /path/to/configs] [-o /path/to/include]
8 SPDX-License-Identifier: Apache 2.0
40 * SPDX-License-Identifier: Apache 2.0
58 memories = f"({'-'.join((str(m).lower() for m in variant['memories']))})"
59 return f"{series}{pincode}{memories}xx-pinctrl.h"
72 m = re.match(r"P([A-Z])(\d+)", pin_name)
93 f.write(f"\n#include \"{series}xx-afio.h\"\n")
94 for signal, cfg in pin_cfgs.items():
95 f.write(f"\n/* {signal} */\n")
97 define = f"#define {signal}_P{port}{pin}{name_suffix}"
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/hal_gigadevice-latest/scripts/tests/gd32pinctrl/data/
Dgd32f888xx.yml2 # SPDX-License-Identifier: Apache 2.0
9 - pincode: X
11 - pincode: X
13 - pincode: Y
16 signal-configs:
18 exclude-memories: [2, 3]
20 exclude-memories: [2, 3]
22 exclude-pincodes: [X]
24 exclude-pincodes: [Y]
25 exclude-memories: [2, 3]
Dgd32f999xx.yml2 # SPDX-License-Identifier: Apache 2.0
9 - pincode: X
11 - pincode: X
13 - pincode: Y
16 signal-configs:
23 exclude-pincodes: [Y]
26 exclude-memories: [2, 3]
29 exclude-memories: [2, 3]
32 exclude-memories: [2, 3]
35 exclude-memories: [2, 3]