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/Zephyr-Core-3.5.0/drivers/crypto/
DKconfig25 bool "TinyCrypt shim driver [EXPERIMENTAL]"
34 Enable TinyCrypt shim layer compliant with crypto APIs.
37 int "Maximum of sessions TinyCrypt shim driver can handle"
52 bool "MbedTLS shim driver [EXPERIMENTAL]"
57 Enable mbedTLS shim layer compliant with crypto APIs. You will need
68 int "Maximum of sessions mbedTLS shim driver can handle"
Dcrypto_tc_shim.c8 * @file Shim layer for TinyCrypt, making it complaint to crypto API.
202 /* The shim currently supports only CBC or CTR mode for AES */ in tc_session_setup()
204 LOG_ERR("TC Shim Unsupported algo"); in tc_session_setup()
218 LOG_ERR("TC Shim Unsupported key size"); in tc_session_setup()
239 LOG_ERR("TC Shim Unsupported mode"); in tc_session_setup()
260 LOG_ERR("TC Shim Unsupported mode"); in tc_session_setup()
/Zephyr-Core-3.5.0/drivers/dma/
Ddma_intel_adsp_gpdma.c52 uint32_t shim; member
64 cap = dw_read(dev_cfg->shim, 0x0); in intel_adsp_gpdma_dump_registers()
65 ctl = dw_read(dev_cfg->shim, 0x4); in intel_adsp_gpdma_dump_registers()
66 ipptr = dw_read(dev_cfg->shim, 0x8); in intel_adsp_gpdma_dump_registers()
67 llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_dump_registers()
68 llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel)); in intel_adsp_gpdma_dump_registers()
69 llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel)); in intel_adsp_gpdma_dump_registers()
93 dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), in intel_adsp_gpdma_llp_config()
105 val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_llp_enable()
107 dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), in intel_adsp_gpdma_llp_enable()
[all …]
/Zephyr-Core-3.5.0/drivers/flash/
DKconfig.rv32m15 bool "RV32M1 flash shim driver"
11 Enables the RV32M1 flash shim driver.
DKconfig.lpc5 bool "LPC flash shim driver"
12 Enables the LPC IAP flash shim driver.
DKconfig.mcux4 bool "MCUX flash shim driver"
15 Enables the MCUX flash shim driver.
/Zephyr-Core-3.5.0/dts/xtensa/intel/
Dintel_adsp_cavs18.dtsi55 compatible = "intel,adsp-shim-clkctl";
65 shim: shim@71f00 { label
66 compatible = "intel,adsp-shim";
71 syscon = <&shim>;
Dintel_adsp_cavs20.dtsi55 compatible = "intel,adsp-shim-clkctl";
65 shim: shim@71f00 { label
66 compatible = "intel,adsp-shim";
99 syscon = <&shim>;
Dintel_adsp_cavs20_jsl.dtsi44 shim: shim@71f00 { label
45 compatible = "intel,adsp-shim";
51 syscon = <&shim>;
Dintel_adsp_cavs15.dtsi59 compatible = "intel,adsp-shim-clkctl";
68 shim: shim@1000 { label
69 compatible = "intel,adsp-shim";
108 syscon = <&shim>;
172 shim = <0x00000c00 0x080>;
185 shim = <0x00000c80 0x080>;
335 shim = <0x1000>;
344 shim = <0x1000>;
Dintel_adsp_cavs25_tgph.dtsi76 compatible = "intel,adsp-shim-clkctl";
95 shim: shim@71f00 { label
96 compatible = "intel,adsp-shim";
129 syscon = <&shim>;
208 shim = <0x71E80>;
217 shim = <0x71E80>;
Dintel_adsp_cavs.dtsi15 shim = <0x00078400 0x100>;
28 shim = <0x00078500 0x100>;
Dintel_adsp_cavs25.dtsi90 compatible = "intel,adsp-shim-clkctl";
109 shim: shim@71f00 { label
110 compatible = "intel,adsp-shim";
143 syscon = <&shim>;
415 shim = <0x71E80>;
424 shim = <0x71E80>;
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-1.5.rst54 - Added DMA QMSI shim driver.
162 * ``ZEP-430`` - Add driver API reentrancy support to PWM shim driver
164 * ``ZEP-440`` - Add driver API reentrancy support to WDT shim driver
165 * ``ZEP-441`` - Add driver API reentrancy support to GPIO shim drivers
178 * ``ZEP-652`` - QMSI shim driver: RTC: Implement suspend and resume callbacks
179 * ``ZEP-655`` - QMSI shim driver: PWM: Implement suspend and resume callbacks
180 * ``ZEP-658`` - QMSI shim driver: GPIO: Implement suspend and resume callbacks
181 * ``ZEP-659`` - QMSI shim driver: UART: Implement suspend and resume callbacks
182 * ``ZEP-662`` - QMSI shim driver: Pinmux: Implement suspend and resume callbacks
249 * ``ZEP-645`` - ARC QMSI ADC shim driver fails to read sample data
Drelease-notes-1.6.rst79 * I2C: Added KSDK shim driver.
80 * Ethernet: Added KSDK shim driver.
81 * Flash: Added KSDK shim driver
83 * QMSI: Implemented suspend and resume functions QMSI shim drivers
199 * ``ZEP-653`` - QMSI shim driver: Watchdog: Implement suspend and resume callbacks
200 * ``ZEP-654`` - QMSI shim driver: I2C: Implement suspend and resume callbacks
201 * ``ZEP-657`` - QMSI shim driver: AONPT: Implement suspend and resume callbacks
202 * ``ZEP-661`` - QMSI shim driver: SPI: Implement suspend and resume callbacks
206 * ``ZEP-717`` - Add ksdk I2C shim driver
207 * ``ZEP-718`` - Add ksdk ethernet shim driver
[all …]
/Zephyr-Core-3.5.0/dts/bindings/i2s/
Dintel,ssp-sspbase.yaml5 description: Intel SSP SHIM controller
/Zephyr-Core-3.5.0/dts/bindings/dai/
Dintel,adsp-dmic-vss.yaml5 description: Intel DMIC Vendor SHIM controller
Dintel,dai-dmic.yaml14 shim:
/Zephyr-Core-3.5.0/drivers/gpio/
DKconfig.sedi13 This driver is simply a shim driver built upon the SEDI
/Zephyr-Core-3.5.0/drivers/serial/
DKconfig.sedi14 This driver is simply a shim driver built upon the SEDI
/Zephyr-Core-3.5.0/drivers/i2c/
DKconfig.sedi13 This driver is simply a shim driver built upon the SEDI
/Zephyr-Core-3.5.0/drivers/ipm/
DKconfig.sedi10 This driver is simply a shim driver built upon the SEDI
/Zephyr-Core-3.5.0/dts/bindings/dma/
Dintel,adsp-gpdma.yaml11 shim:
/Zephyr-Core-3.5.0/modules/hal_nordic/nrf_802154/serialization/platform/
Dnrf_802154_init_net.c14 /* On NET core we don't use Zephyr's shim layer so we have to call inits manually */ in serialization_init()
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/
Dadsp_shim.h9 /* The "shim" block contains most of the general system control
54 #define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
88 /* Host memory window control. Not strictly part of the shim block. */

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