Searched +full:sgmii +full:- +full:mode (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-latest/dts/bindings/ethernet/ |
| D | xlnx,gem.yaml | 3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
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| /Zephyr-latest/boards/nxp/ls1046ardb/doc/ |
| D | index.rst | 6 The LS1046A reference design board (RDB) is a high-performance computing,
10 of high-speed SerDes ports.
12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13 cores with packet processing acceleration and high-speed peripherals. The
25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26 - Supports 8 GB DDR4 SDRAM memory
27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
29 - One 512 MB SLC NAND flash with ECC support (1.8 V)
30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31 - Support two 64 MB onboard QSPI NOR flash memories
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_cyclonev_priv.h | 4 * SPDX-License-Identifier: Apache-2.0
8 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
123 #define EMAC_DMAGRP_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMA_MODE_OFST) /* Bus Mode */
129 /* Operation Mode */
135 /* AXI Bus Mode */
142 /* SGMII RGMII SMII Control Status */
179 /* Bus Mode */
196 /* Operation Mode */
236 /* AXI Bus Mode */
259 /* SGMII RGMII SMII Control Status */
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| D | eth_xlnx_gem_priv.h | 7 * SPDX-License-Identifier: Apache-2.0
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
56 * [13] FCS status bit for FCS ignore mode
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
86 * exhausted mid-frame
116 * Zynq-7000 TX clock configuration:
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| D | eth_xlnx_gem.c | 5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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