| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_rcu.c | 133 \arg RCU_ENET: ENET clock(EPRT and CL series available)
134 \arg RCU_ENETTX: ENETTX clock(EPRT and CL series available)
135 \arg RCU_ENETRX: ENETRX clock(EPRT and CL series available)
136 \arg RCU_USBD: USBD clock(HD,XD and EPRT series available)
137 \arg RCU_USBHS: USBHS clock(CL series available)
141 …IMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for EPRT series): TIMER clock
147 …\arg RCU_CANx (x=0,1,2,CAN2 is only available for CL series,CANx is not avaliable for GD32E…
151 \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
152 \arg RCU_SDIO: SDIO clock(not available for CL and EPRT series)
155 \arg RCU_SHRTIMER: (not available for EPRT series):SHRTIMER clock
[all …]
|
| D | gd32e50x_dbg.c | 99 …\arg DBG_CANx_HOLD (x=0,1,2 CAN2 is only available for CL series): hold CANx receive regist…
101 …,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for GD32EPRT series): hold TIMERx coun…
102 …rg DBG_SHRTIMER_HOLD : hold SHRTIMER counter when core is halted, except for GD32EPRT series
117 …\arg DBG_CANx_HOLD (x=0,1,2 CAN2 is only available for CL series): hold CANx receive regist…
119 …,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for GD32EPRT series): hold TIMERx coun…
120 …rg DBG_SHRTIMER_HOLD : hold SHRTIMER counter when core is halted, except for GD32EPRT series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/scripts/ |
| D | gd32pinctrl.py | 46 def get_header_fname(series, variant): argument
50 series: Series.
59 return f"{series}{pincode}{memories}xx-pinctrl.h"
79 def generate_afio_header(outdir, variant, series, pin_cfgs): argument
85 series: Series.
91 with open(outdir / get_header_fname(series, variant), "w") as f:
93 f.write(f"\n#include \"{series}xx-afio.h\"\n")
102 def generate_af_header(outdir, variant, series, pin_cfgs): argument
108 series: Series.
114 with open(outdir / get_header_fname(series, variant), "w") as f:
[all …]
|
| D | gd32headers.py | 31 # obtain all available APIs for each series
37 # obtain series API headers
67 for i, series in enumerate(all_series):
69 f.write(f" defined(CONFIG_SOC_SERIES_{series.upper()})\n")
70 f.write(f"#include <{series}_{api}.h>\n")
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/pinconfigs/ |
| D | README.md | 29 - `series` (required): Series name, e.g. gd32vf103
39 series: gd32vf103
164 For GD32F405Vx series, LQFP100 package have 82 I/O pins, but BGA100 package only have 81 I/O pins. …
|
| D | gd32f350xx.yml | 26 series: gd32f350
|
| D | gd32a503xx.yml | 24 series: gd32a503
|
| D | gd32f405xx.yml | 23 series: gd32f405
|
| D | gd32l233xx.yml | 25 series: gd32l233
|
| D | gd32vf103xx.yml | 26 series: gd32vf103
|
| D | gd32f407xx.yml | 24 series: gd32f407
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_dbg.c | 87 …\arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when cor…
89 …D (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx coun…
104 …\arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when cor…
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/scripts/tests/gd32pinctrl/data/ |
| D | gd32f888xx.yml | 6 series: gd32f888
|
| D | gd32f999xx.yml | 6 series: gd32f999
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/riscv/include/ |
| D | system_gd32vf103.h | 4 GD32VF103 Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/cmsis/gd/gd32f3x0/include/ |
| D | system_gd32f3x0.h | 4 GD32F3x0 Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/cmsis/gd/gd32e10x/include/ |
| D | system_gd32e10x.h | 4 GD32E10x Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/cmsis/gd/gd32e50x/include/ |
| D | system_gd32e50x.h | 4 GD32E50x Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/cmsis/gd/gd32l23x/include/ |
| D | system_gd32l23x.h | 4 GD32L23x Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/cmsis/gd/gd32a50x/include/ |
| D | system_gd32a50x.h | 4 GD32A50X Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/cmsis/gd/gd32f403/include/ |
| D | system_gd32f403.h | 4 GD32F403 Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/cmsis/gd/gd32f4xx/include/ |
| D | system_gd32f4xx.h | 4 GD32F4xx Device Series
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/cmsis/gd/gd32e50x/source/ |
| D | system_gd32e50x.c | 4 GD32E50x Device Series
53 /* use HXTAL(EPRT/HD/XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/cmsis/gd/gd32f403/source/ |
| D | system_gd32f403.c | 4 GD32F403 Device Series
55 /* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
|
| /hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/cmsis/gd/gd32l23x/source/ |
| D | system_gd32l23x.c | 4 GD32L23x Device Series
|
