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/hal_nxp-latest/mcux/mcux-sdk/drivers/src/
Dfsl_src.h178 base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA); in SRC_EnableWDOG3Reset()
182 base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5); in SRC_EnableWDOG3Reset()
196 base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option); in SRC_SetMixResetStretchCycles()
211 base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK; in SRC_EnableCoreDebugResetAfterPowerGate()
215 base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK; in SRC_EnableCoreDebugResetAfterPowerGate()
229 base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option); in SRC_SetWdog3ResetOption()
241 base->SCR |= SRC_SCR_CORES_DBG_RST_MASK; in SRC_DoSoftwareResetARMCoreDebug()
251 return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK)); in SRC_GetSoftwareResetARMCoreDebugDone()
269 base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2); in SRC_EnableTemperatureSensorReset()
273 base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5); in SRC_EnableTemperatureSensorReset()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC824/drivers/
Dfsl_power.c31 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
32 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
60 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
66 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
67 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
91 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
92 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
97 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
98 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC822/drivers/
Dfsl_power.c31 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
32 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
60 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
66 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
67 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
91 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
92 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
97 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
98 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC834/drivers/
Dfsl_power.c31 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
32 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
60 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
66 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
67 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
91 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
92 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
97 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
98 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC832/drivers/
Dfsl_power.c31 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
32 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
60 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
66 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
67 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
91 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
92 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
97 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
98 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC845/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC812/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC804/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC844/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
63 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
64 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
69 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
70 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
94 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
95 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
100 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
101 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC810/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC811/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
63 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
64 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
69 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
70 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
94 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
95 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
100 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
101 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC802/drivers/
Dfsl_power.c34 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterSleep()
35 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterSleep()
64 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
65 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
70 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterDeepSleep()
71 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterDeepSleep()
95 /* enable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
96 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
101 /* disable Deepsleep mode in the ARM-CORTEX M0+ SCR register */ in POWER_EnterPowerDown()
102 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in POWER_EnterPowerDown()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/cmp/
Dfsl_cmp.c213 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_EnableDMA()
223 base->SCR = tmp8; in CMP_EnableDMA()
293 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_EnableInterrupts()
303 base->SCR = tmp8; in CMP_EnableInterrupts()
314 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_DisableInterrupts()
324 base->SCR = tmp8; in CMP_DisableInterrupts()
338 if (0U != (CMP_SCR_CFR_MASK & base->SCR)) in CMP_GetStatusFlags()
342 if (0U != (CMP_SCR_CFF_MASK & base->SCR)) in CMP_GetStatusFlags()
346 if (0U != (CMP_SCR_COUT_MASK & base->SCR)) in CMP_GetStatusFlags()
361 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_ClearStatusFlags()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011_features.h519 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
521 /* @brief There is MIX_RST_STRCH bit in SCR register. */
523 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
525 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
527 /* @brief There is CORES_DBG_RST bit in SCR register. */
529 /* @brief There is MTSR bit in SCR register. */
531 /* @brief There is CORE0_DBG_RST bit in SCR register. */
533 /* @brief There is CORE0_RST bit in SCR register. */
535 /* @brief There is LOCKUP_RST bit in SCR register. */
537 /* @brief There is SWRC bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015_features.h530 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
532 /* @brief There is MIX_RST_STRCH bit in SCR register. */
534 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
536 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
538 /* @brief There is CORES_DBG_RST bit in SCR register. */
540 /* @brief There is MTSR bit in SCR register. */
542 /* @brief There is CORE0_DBG_RST bit in SCR register. */
544 /* @brief There is CORE0_RST bit in SCR register. */
546 /* @brief There is LOCKUP_RST bit in SCR register. */
548 /* @brief There is SWRC bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064_features.h234 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
731 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
733 /* @brief There is MIX_RST_STRCH bit in SCR register. */
735 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
737 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
739 /* @brief There is CORES_DBG_RST bit in SCR register. */
741 /* @brief There is MTSR bit in SCR register. */
743 /* @brief There is CORE0_DBG_RST bit in SCR register. */
745 /* @brief There is CORE0_RST bit in SCR register. */
747 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062_features.h236 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
733 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
735 /* @brief There is MIX_RST_STRCH bit in SCR register. */
737 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
739 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
741 /* @brief There is CORES_DBG_RST bit in SCR register. */
743 /* @brief There is MTSR bit in SCR register. */
745 /* @brief There is CORE0_DBG_RST bit in SCR register. */
747 /* @brief There is CORE0_RST bit in SCR register. */
749 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041_features.h220 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
691 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
693 /* @brief There is MIX_RST_STRCH bit in SCR register. */
695 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
697 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
699 /* @brief There is CORES_DBG_RST bit in SCR register. */
701 /* @brief There is MTSR bit in SCR register. */
703 /* @brief There is CORE0_DBG_RST bit in SCR register. */
705 /* @brief There is CORE0_RST bit in SCR register. */
707 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042_features.h224 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
721 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
723 /* @brief There is MIX_RST_STRCH bit in SCR register. */
725 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
727 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
729 /* @brief There is CORES_DBG_RST bit in SCR register. */
731 /* @brief There is MTSR bit in SCR register. */
733 /* @brief There is CORE0_DBG_RST bit in SCR register. */
735 /* @brief There is CORE0_RST bit in SCR register. */
737 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061_features.h230 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
701 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
703 /* @brief There is MIX_RST_STRCH bit in SCR register. */
705 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
707 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
709 /* @brief There is CORES_DBG_RST bit in SCR register. */
711 /* @brief There is MTSR bit in SCR register. */
713 /* @brief There is CORE0_DBG_RST bit in SCR register. */
715 /* @brief There is CORE0_RST bit in SCR register. */
717 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021_features.h216 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
682 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
684 /* @brief There is MIX_RST_STRCH bit in SCR register. */
686 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
688 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
690 /* @brief There is CORES_DBG_RST bit in SCR register. */
692 /* @brief There is MTSR bit in SCR register. */
694 /* @brief There is CORE0_DBG_RST bit in SCR register. */
696 /* @brief There is CORE0_RST bit in SCR register. */
698 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024_features.h214 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
680 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
682 /* @brief There is MIX_RST_STRCH bit in SCR register. */
684 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
686 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
688 /* @brief There is CORES_DBG_RST bit in SCR register. */
690 /* @brief There is MTSR bit in SCR register. */
692 /* @brief There is CORE0_DBG_RST bit in SCR register. */
694 /* @brief There is CORE0_RST bit in SCR register. */
696 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051_features.h224 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
695 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
697 /* @brief There is MIX_RST_STRCH bit in SCR register. */
699 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
701 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
703 /* @brief There is CORES_DBG_RST bit in SCR register. */
705 /* @brief There is MTSR bit in SCR register. */
707 /* @brief There is CORE0_DBG_RST bit in SCR register. */
709 /* @brief There is CORE0_RST bit in SCR register. */
711 /* @brief There is LOCKUP_RST bit in SCR register. */
[all …]

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