Searched full:sam (Results 1 – 25 of 28) sorted by relevance
12
| /trusted-firmware-m-latest/platform/ext/target/arm/drivers/sam/ |
| D | sam_drv.h | 19 * \brief Driver for Arm Security Alarm Manager (SAM).
34 * \brief SAM Event IDs.
97 * \brief SAM response action IDs.
114 * \brief SAM error type.
122 * \brief SAM event handler function type.
126 /* SAM config covers 24 registers: samem to samicv */
130 * \brief SAM device configuration structure.
133 const uintptr_t base; /**< SAM base address */
134 const uint32_t default_config[SAM_CONFIG_LEN]; /**< Default SAM config */
138 * \brief SAM device structure.
[all …]
|
| D | sam_reg_map.h | 10 * \brief Register map of Arm Security Alarm Manager (SAM).
23 * \brief SAM register map.
27 /**< Offset: 0x000 (R/ ) SAM Build Configuration register */
29 /**< Offset: 0x004 (R/ ) SAM Event Status registers */
31 /**< Offset: 0x00C ( /W) SAM Event Clear registers */
33 /**< Offset: 0x014 (R/W) SAM Export Mask registers */
35 /**< Offset: 0x01C (R/W) SAM Input Mask registers */
37 /**< Offset: 0x024 (R/W) SAM Response Routing Logic Setup registers */
39 /**< Offset: 0x044 (R/W) SAM Event Counter registers */
41 /**< Offset: 0x064 (R/W) SAM Event Counters Timer Initial Value register */
[all …]
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/bl1/scripts/include/ |
| D | program5_cmd0.yaml | 8 # This command loads the SAM configuration from OTP into the SAM registers
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/ |
| D | target_cfg.c | 211 /* Make sure that SAM interrupts target S state */ in nvic_interrupt_target_state_cfg()
258 /* Enable SAM interrupts. Set SAM critical security fault to the highest in nvic_interrupt_enable()
259 * priority and other SAM faults to one lower priority. in nvic_interrupt_enable()
271 /* Set the SAM watchdog counter to trigger if NMI, Critical Sec Fault in nvic_interrupt_enable()
|
| D | CMakeLists.txt | 137 ${PLATFORM_DIR}/ext/target/arm/drivers/sam
172 ${PLATFORM_DIR}/ext/target/arm/drivers/sam/sam_drv.c
290 ${PLATFORM_DIR}/ext/target/arm/drivers/sam
361 ${PLATFORM_DIR}/ext/target/arm/drivers/sam
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/bl1/scripts/ |
| D | dma_config.yaml | 23 sam:
97 description: "Copy SAM configuration"
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/device/include/ |
| D | platform_irq.h | 60 SAM_Critical_Sec_Fault_S_IRQn = 32, /* SAM Critical Security Fault (Secure) Interrupt */
61 SAM_Sec_Fault_S_IRQn = 33, /* SAM Security Fault (Secure) Interrupt */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/provisioning/bundle_cm/ |
| D | cm_provisioning_data_template.jinja2 | 17 /* SAM config */
|
| D | cm_provisioning_config.cmake | 19 0x00000000," CACHE STRING "SAM Configuration with ICV")
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/include/ |
| D | platform_irq.h | 65 SAM_CRITICAL_SEVERITY_FAULT_IRQn = 30, /* SAM Critical Severity Fault Interrupt */
66 SAM_SEVERITY_FAULT_HANDLER_IRQn = 31, /* SAM Severity Fault Handler Interrupt */
|
| D | platform_s_device_definition.h | 105 /* SAM driver structure */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/config/ |
| D | device_cfg.h | 42 /* Arm SAM */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/rdfremont/ |
| D | rse_memory_sizes.h | 45 /* How much space in OTP can be used for the SAM configuration */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/tc/ |
| D | rse_memory_sizes.h | 44 /* How much space in OTP can be used for the SAM configuration */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/kronos/ |
| D | rse_memory_sizes.h | 45 /* How much space in OTP can be used for the SAM configuration */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/device/config/ |
| D | device_cfg.h | 100 /* Arm SAM */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/device/source/ |
| D | startup_rse_bl.c | 123 invalid_irq_handler, /* 32: SAM Critical Security Fault (Secure) Handler */
124 invalid_irq_handler, /* 33: SAM Security Fault (Secure) Handler */
|
| D | startup_rse.c | 180 SAM_Critical_Sec_Fault_S_Handler, /* 32: SAM Critical Security Fault (Secure) Handler */
181 SAM_Sec_Fault_S_Handler, /* 33: SAM Security Fault (Secure) Handler */
|
| D | device_definition.c | 573 /* Default SAM config that enables all events and sets all response actions
591 * the rest of the SAM config.
|
| D | startup_rse_bl1_1.c | 128 invalid_irq_handler, /* 32: SAM Critical Security Fault (Secure) Handler */
129 invalid_irq_handler, /* 33: SAM Security Fault (Secure) Handler */
|
| /trusted-firmware-m-latest/docs/platform/arm/rse/rom_releases/2024-04/ |
| D | readme.rst | 23 - Allows for setup of SAM configuration with provisioned values before CPU is
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/source/ |
| D | platform_s_device_definition.c | 591 /* Default SAM config that enables all events and sets all response actions
609 * the rest of the SAM config.
|
| D | startup_corstone315.c | 183 SAM_Critical_Severity_Fault_Handler, /* 30: SAM Critical Severity Fault Handler */
184 SAM_Severity_Fault_Handler, /* 31: SAM Severity Fault Handler */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/bl1/ |
| D | boot_hal_bl1_1.c | 228 /* SAM registers can only be accessed with 32bit read/write instructions. in load_sam_config()
|
| /trusted-firmware-m-latest/docs/platform/arm/mps4/corstone315/ |
| D | README.rst | 8 an Armv8.1-M Cortex-M85 processor and LCM, KMU and SAM IPs. and an
|
12
