Home
last modified time | relevance | path

Searched full:rw (Results 1 – 25 of 122) sorted by relevance

12345

/Zephyr-latest/samples/modules/canopennode/objdict/
Dobjdict.eds189 AccessType=rw
270 AccessType=rw
279 AccessType=rw
288 AccessType=rw
339 AccessType=rw
363 AccessType=rw
390 AccessType=rw
414 AccessType=rw
423 AccessType=rw
432 AccessType=rw
[all …]
Dobjdict.xml21 …ror field" objectType="ARRAY" memoryType="RAM" dataType="0x07" accessType="rw" PDOmapping="no" def…
28 …="00" name="Number of errors" objectType="VAR" dataType="0x05" accessType="rw" PDOmapping="no" def…
57 …YNC message" objectType="VAR" memoryType="ROM" dataType="0x07" accessType="rw" PDOmapping="no" def…
63 …ycle period" objectType="VAR" memoryType="ROM" dataType="0x07" accessType="rw" PDOmapping="no" def…
66 …ndow length" objectType="VAR" memoryType="ROM" dataType="0x07" accessType="rw" PDOmapping="no" def…
92 …arameters" objectType="ARRAY" memoryType="RAM" dataType="0x07" accessType="rw" PDOmapping="no" sub…
97 …1" name="save all parameters" objectType="VAR" dataType="0x00" accessType="rw" PDOmapping="no" def…
101 …arameters" objectType="ARRAY" memoryType="RAM" dataType="0x07" accessType="rw" PDOmapping="no" sub…
106 …store all default parameters" objectType="VAR" dataType="0x00" accessType="rw" PDOmapping="no" def…
116 … time stamp" objectType="VAR" memoryType="RAM" dataType="0x07" accessType="rw" PDOmapping="no" def…
[all …]
/Zephyr-latest/tests/net/lib/lwm2m/lwm2m_registry/src/
Dtest_obj.c35 OBJ_FIELD(LWM2M_RES_TYPE_OPAQUE, RW, OPAQUE),
36 OBJ_FIELD(LWM2M_RES_TYPE_STRING, RW, STRING),
37 OBJ_FIELD(LWM2M_RES_TYPE_U32, RW, U32),
38 OBJ_FIELD(LWM2M_RES_TYPE_U16, RW, U16),
39 OBJ_FIELD(LWM2M_RES_TYPE_U8, RW, U8),
40 OBJ_FIELD(LWM2M_RES_TYPE_S64, RW, S64),
41 OBJ_FIELD(LWM2M_RES_TYPE_S32, RW, S32),
42 OBJ_FIELD(LWM2M_RES_TYPE_S16, RW, S16),
43 OBJ_FIELD(LWM2M_RES_TYPE_S8, RW, S8),
44 OBJ_FIELD(LWM2M_RES_TYPE_BOOL, RW, BOOL),
[all …]
/Zephyr-latest/arch/arm/core/cortex_m/cmse/
Darm_core_cmse.c21 static int arm_cmse_addr_read_write_ok(uint32_t addr, int force_npriv, int rw) in arm_cmse_addr_read_write_ok() argument
30 return rw ? addr_info.flags.readwrite_ok : addr_info.flags.read_ok; in arm_cmse_addr_read_write_ok()
44 int force_npriv, int rw) in arm_cmse_addr_range_read_write_ok() argument
51 if (rw) { in arm_cmse_addr_range_read_write_ok()
116 int force_npriv, int rw) in arm_cmse_addr_nonsecure_read_write_ok() argument
125 return rw ? addr_info.flags.nonsecure_readwrite_ok : in arm_cmse_addr_nonsecure_read_write_ok()
140 int force_npriv, int rw) in arm_cmse_addr_range_nonsecure_read_write_ok() argument
147 if (rw) { in arm_cmse_addr_range_nonsecure_read_write_ok()
/Zephyr-latest/dts/bindings/arm/
Dnxp,rw-soc-ctrl.yaml4 description: RW SOC controller node
6 compatible: "nxp,rw-soc-ctrl"
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dcomm_widget.h183 * type: RW, rst: 0b, rst domain: gHSTRST
279 * type: RW, rst: 0b, rst domain: gHSTRST
289 * type: RW/1C, rst: 0b, rst domain: gHSTRST
315 * type: RW/1C, rst: 0b, rst domain: gHSTRST
349 * type: RW, rst: 0b, rst domain: gHSTRST
360 * type: RW, rst: 0b, rst domain: gHSTRST
369 * type: RW, rst: 0b, rst domain: gHSTRST
387 * type: RW, rst: 0000 0000h, rst domain: gHSTRST
403 * type: RW, rst: 0000h, rst domain: gHSTRST
418 * type: RW, rst: 0b, rst domain: gHSTRST
[all …]
Dtimestamp.c51 /* Clear NTK (RW/1C) bit if needed */ in intel_adsp_get_timestamp()
89 /* Clear NTK (RW/1C) bit */ in intel_adsp_get_timestamp()
/Zephyr-latest/dts/bindings/power/
Dnxp,rw-pmu.yaml4 description: NXP RW PMU
6 compatible: "nxp,rw-pmu"
/Zephyr-latest/drivers/i2c/
Di2c_andes_atciic100.h45 /* Interrupt Enable Register(RW) */
58 /* Status Register(RW) */
76 /* Control Register(RW) */
84 /* Command Register(RW) */
93 /* Setup Register(RW) */
/Zephyr-latest/soc/renesas/smartbond/da1469x/
Dintvect_reserved.ld9 /* Access to addresses in range 0x0-0x1ff is remapped to sram to allow rw
/Zephyr-latest/soc/neorv32/
Dlinker.ld11 IO (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_pcr.h286 * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287 * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
289 * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
295 * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
299 /* Clock monitor control register (Offset +0xE0, RW) */
317 /* Clock monitor interrupt enable (Offset +0xE8, RW) */
/Zephyr-latest/drivers/mdio/
Dmdio_litex_liteeth.c98 static int mdio_litex_transfer(const struct device *dev, uint8_t prtad, uint8_t devad, uint8_t rw, in mdio_litex_transfer() argument
112 mdio_litex_write(dev_cfg, rw ? 0x1 : 0x2, 2); in mdio_litex_transfer()
118 if (rw) { /* Write data */ in mdio_litex_transfer()
Dmdio_gpio.c76 static int mdio_gpio_transfer(const struct device *dev, uint8_t prtad, uint8_t devad, uint8_t rw, in mdio_gpio_transfer() argument
91 mdio_gpio_write(dev_cfg, rw ? 0x1 : 0x2, 2); in mdio_gpio_transfer()
97 if (rw) { /* Write data */ in mdio_gpio_transfer()
/Zephyr-latest/drivers/watchdog/
Dwdt_intel_adsp.h38 * type: RW/1C, rst: 0b, rst domain: DSPLRST
47 * type: RW/1S, rst: 0b, rst domain: DSPLRST
134 * type: RW/1S, rst: 0b, rst domain: DSPLRST
/Zephyr-latest/tests/subsys/fs/littlefs/
DCMakeLists.txt8 # LittleFS opens files for RW by default if no flags given and crashes,
/Zephyr-latest/drivers/smbus/
Dintel_pch_smbus.c366 uint8_t rw, uint8_t command, uint8_t count, in pch_smbus_block_start() argument
372 LOG_DBG("addr %x rw %d command %x", periph_addr, rw, command); in pch_smbus_block_start()
376 reg |= rw & SMBUS_MSG_RW_MASK; in pch_smbus_block_start()
394 if (rw == SMBUS_MSG_WRITE) { in pch_smbus_block_start()
420 enum smbus_direction rw, uint8_t command, in pch_smbus_start() argument
426 LOG_DBG("addr 0x%02x rw %d command %x", periph_addr, rw, command); in pch_smbus_start()
430 reg |= rw & SMBUS_MSG_RW_MASK; in pch_smbus_start()
439 if (rw == SMBUS_MSG_WRITE && protocol != SMBUS_CMD_BYTE) { in pch_smbus_start()
468 enum smbus_direction rw) in pch_smbus_quick() argument
473 LOG_DBG("dev %p addr 0x%02x direction %x", dev, periph_addr, rw); in pch_smbus_quick()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_max149x6.h88 uint8_t *rx_diag_buff, uint8_t rw) in max149x6_reg_transceive() argument
116 FIELD_PREP(MAX149x6_RW_MASK, rw & 0x1); in max149x6_reg_transceive()
148 if ((MAX149x6_WRITE == rw) && (rx_diag_buff != NULL)) { in max149x6_reg_transceive()
/Zephyr-latest/samples/drivers/memc/boards/
Dfrdm_rw612.conf4 # In order to safely access the PSRAM on port B of the RW FlexSPI peripheral,
Drd_rw612_bga.conf4 # In order to safely access the PSRAM on port B of the RW FlexSPI peripheral,
/Zephyr-latest/soc/intel/intel_ish/utils/
Dbuild_ish_firmware.py26 usually ec.RW.bin or ec.RW.flat.",
/Zephyr-latest/lib/posix/options/
Dmmap.c24 bool rw = (prot & PROT_WRITE) != 0; in p2z() local
34 return (rw * K_MEM_PERM_RW) | (ex * K_MEM_PERM_EXEC) | (fixed * K_MEM_DIRECT_MAP); in p2z()
/Zephyr-latest/boards/nxp/frdm_rw612/
Dfrdm_rw612-pinctrl.dtsi7 #include <nxp/rw/RW612-pinctrl.h>
/Zephyr-latest/tests/net/lib/lwm2m/content_json/src/
Dmain.c30 OBJ_FIELD_DATA(TEST_RES_S8, RW, S8),
31 OBJ_FIELD_DATA(TEST_RES_S16, RW, S16),
32 OBJ_FIELD_DATA(TEST_RES_S32, RW, S32),
33 OBJ_FIELD_DATA(TEST_RES_S64, RW, S64),
34 OBJ_FIELD_DATA(TEST_RES_STRING, RW, STRING),
35 OBJ_FIELD_DATA(TEST_RES_FLOAT, RW, FLOAT),
36 OBJ_FIELD_DATA(TEST_RES_BOOL, RW, BOOL),
37 OBJ_FIELD_DATA(TEST_RES_OBJLNK, RW, OBJLNK),
/Zephyr-latest/arch/arm/include/cortex_m/
Dcmse.h85 * @param addr The address for which the RW ability is requested
86 * @param force_npriv Instruct to return the RW ability of the address
128 * for which the RW ability is requested
130 * @param force_npriv Instruct to return the RW ability of the address range
316 * @param addr The address for which the RW ability is requested
317 * @param force_npriv Instruct to return the RW ability of the address

12345