| /Zephyr-Core-3.6.0/drivers/reset/ |
| D | Kconfig | 1 # Reset Controller driver configuration options
7 # Reset Controller options
9 menuconfig RESET config
10 bool "Reset Controller drivers"
12 Reset Controller drivers. Reset node represents a region containing
13 information about reset controller device. The typical use-case is
14 for some other node's drivers to acquire a reference to the reset
15 controller node together with some reset information.
17 if RESET
20 int "Reset Controller driver init priority"
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| /Zephyr-Core-3.6.0/include/zephyr/devicetree/ |
| D | reset.h | 3 * @brief Reset Controller Devicetree macro public API header file.
20 * @defgroup devicetree-reset-controller Devicetree Reset Controller API
31 * reset1: reset-controller@... { ... };
33 * reset2: reset-controller@... { ... };
46 * @return the node identifier for the reset controller referenced at
56 * @return a node identifier for the reset controller at index 0
69 * reset1: reset-controller@... { ... };
71 * reset2: reset-controller@... { ... };
75 * reset-names = "alpha", "beta";
85 * as defined by the node's reset-names property
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| /Zephyr-Core-3.6.0/include/zephyr/drivers/ |
| D | reset.h | 9 * @brief Public Reset Controller driver APIs
16 * @brief Reset Controller Interface
17 * @defgroup reset_controller_interface Reset Controller Interface
31 /** Reset controller device configuration. */
33 /** Reset controller device. */
35 /** Reset line. */
43 * devicetree node identifier, a property specifying a Reset Controller and an index.
48 * resets = <&reset 10>;
56 * // .dev = DEVICE_DT_GET(DT_NODELABEL(reset)),
60 * The 'reset' field must still be checked for readiness, e.g. using
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| D | hwinfo.h | 34 * @name Reset cause flags
40 /** Software reset */
44 /** Power-on reset (POR) */
62 /** Hardware reset */
64 /** User reset */
66 /** Temperature reset */
97 * @brief Retrieve cause of device reset.
99 * @param cause OR'd @ref reset_cause "reset cause" flags
101 * This routine retrieves the flags that indicate why the device was reset.
103 * On some platforms the reset cause flags accumulate between successive resets
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| /Zephyr-Core-3.6.0/soc/arm/nxp_s32/ |
| D | Kconfig | 14 int "Functional Reset Escalation threshold"
18 If the value of this option is 0, the Functional reset escalation
20 resets that causes a Destructive reset, if the FRET register isn't
22 Default to maximum threshold (hardware reset value).
25 int "Destructive Reset Escalation threshold"
29 If the value of this field is 0, the Destructive reset escalation
31 resets which keeps the chip in the reset state until the next power-on
32 reset triggers a new reset sequence, if the DRET register isn't
34 Default to disabled (hardware reset value).
|
| /Zephyr-Core-3.6.0/soc/arm/nxp_s32/common/ |
| D | power_soc.c | 16 BUILD_ASSERT(POWER_IP_PERFORM_RESET_API == STD_ON, "Power Reset API must be enabled");
21 * SYS_REBOOT_COLD (Destructive Reset):
22 * - Leads most parts of the chip, except a few modules, to reset. SRAM content
23 * is lost after this reset event.
24 * - Flash is always reset, so an updated value of the option bits is reloaded
27 * - STCU is reset and configured BISTs are executed.
29 * SYS_REBOOT_WARM (Functional Reset):
30 * - Leads all the communication peripherals and cores to reset. The communication
32 * after reset. The SRAM content, and the functionality of certain modules, is
33 * preserved across functional reset.
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| /Zephyr-Core-3.6.0/dts/bindings/reset/ |
| D | gd,gd32-rctl.yaml | 5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the reset controller (RCTL).
9 To specify the reset line in a peripheral, the standard resets property needs
19 Predefined RCU reset cells are available in
20 include/zephyr/dts-bindings/reset/gd32{xxx}.h header files, where {xxx}
25 include: [reset-controller.yaml, base.yaml]
28 "#reset-cells":
31 reset-cells:
|
| D | st,stm32-rcc-rctl.yaml | 5 STM32 Reset and Clock Control (RCC) node.
6 This node is in charge of reset control for AHB (Advanced High Performance)
9 To specify the reset line in a peripheral, the standard resets property needs
19 RCC reset cells are available in
20 include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
24 include: [reset-controller.yaml, base.yaml]
27 "#reset-cells":
34 deassert reset.
36 reset-cells:
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| D | raspberrypi,pico-reset.yaml | 4 description: Raspberry Pi Pico Reset Controller
6 compatible: "raspberrypi,pico-reset"
8 include: [base.yaml, reset-controller.yaml]
15 description: The width of the reset registers in bytes. Default is 4 bytes.
18 description: Set if reset is active low. Default is 0, which means active-high.
19 "#reset-cells":
22 reset-cells:
|
| D | intel,socfpga-reset.yaml | 4 description: Intel SoC FPGA Reset Controller
6 compatible: "intel,socfpga-reset"
8 include: [base.yaml, reset-controller.yaml]
15 description: Add this property in dts node if the reset line is active_low, otherwise do not
17 "#reset-cells":
20 reset-cells:
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| D | aspeed,ast10x0-reset.yaml | 4 description: Aspeed AST10X0 Reset Controller
6 compatible: "aspeed,ast10x0-reset"
8 include: [base.yaml, reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
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| D | reset-device.yaml | 4 description: This file needs to be included by devices that need a reset controller.
9 description: Reset information
11 reset-names:
13 description: Name of each reset
|
| D | nuvoton,numaker-rst.yaml | 4 description: Nuvoton, Numaker-RESET
8 include: [reset-controller.yaml, base.yaml]
14 "#reset-cells":
17 reset-cells:
|
| /Zephyr-Core-3.6.0/doc/hardware/peripherals/ |
| D | reset.rst | 3 Reset Controller
9 Reset controllers are units that control the reset signals to multiple
10 peripherals. The reset controller API allows peripheral drivers to request
11 control over their reset input signals, including the ability to assert,
12 deassert and toggle those signals. Also, the reset status of the reset input
16 in most cases we want to toggle the reset signals.
|
| /Zephyr-Core-3.6.0/samples/drivers/espi/boards/ |
| D | mec172xevb_assy6906.overlay | 24 reset-state = "1";
25 reset-source = "ESPI_RESET";
30 reset-state = "1";
31 reset-source = "ESPI_RESET";
36 reset-state = "1";
37 reset-source = "ESPI_RESET";
42 reset-state = "1";
43 reset-source = "ESPI_RESET";
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| /Zephyr-Core-3.6.0/dts/bindings/test/ |
| D | vnd,reset.yaml | 4 description: Test Reset Controller
6 compatible: "vnd,reset"
8 include: [base.yaml, reset-controller.yaml]
14 "#reset-cells":
17 reset-cells:
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| /Zephyr-Core-3.6.0/drivers/watchdog/ |
| D | Kconfig.smartbond | 14 bool "NMI pre-reset interrupt enable"
20 reset at <= -16. Timer can be frozen/resumed using
24 reset at value 0 and can not be frozen by Software.
26 only be reset with a WDOG (SYS) reset or SW reset.
|
| D | wdt_dw.h | 21 * The generated interrupt is passed to an interrupt controller. The generated reset is passed to a
22 * reset controller, which in turn generates a reset for the components in the system. The WDT may
23 * be reset independently to the other components.
52 /* Generate a system reset
57 * by the time a second timeout occurs then generate a system reset
62 * Reset pulse length
195 * Describes the initial timeout period that is available directly after reset. It controls the
196 * reset value of the register. If WDT_HC_TOP is 1, then the default initial time period is the
202 * Selects the timeout period that is available directly after reset. It controls the reset value
209 * The reset pulse length that is available directly after reset.
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| /Zephyr-Core-3.6.0/dts/bindings/espi/ |
| D | microchip,xec-espi-vw-routing.yaml | 28 reset-state:
31 Optional default virtual wire state on reset (0 or 1).
38 reset-source:
41 Optional reset source in addition to chip reset.
43 and 3 is ESPI Platform Reset. If this property is not
44 present the hardware default is used. Note: reset source
|
| /Zephyr-Core-3.6.0/dts/bindings/flash_controller/ |
| D | st,stm32-qspi-nor.yaml | 13 reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
14 reset-gpios-duration = <1>;
33 reset-gpios:
36 reset-gpios-duration:
38 description: The duration (in ms) for the flash memory reset pulse
39 reset-cmd:
41 description: Send reset command on initialization
42 reset-cmd-wait:
45 description: The duration (in us) to wait after reset command
|
| /Zephyr-Core-3.6.0/dts/arm64/intel/ |
| D | intel_socfpga_agilex5.dtsi | 10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
108 resets = <&reset RSTMGR_UART0_RSTLINE>;
112 reset: reset-controller@10D11000 { label
113 compatible = "intel,socfpga-reset";
116 #reset-cells = <1>;
127 resets = <&reset RSTMGR_SDMMC_RSTLINE>,
128 <&reset RSTMGR_SDMMCECC_RSTLINE>,
129 <&reset RSTMGR_SOFTPHY_RSTLINE>;
140 resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
151 resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
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| /Zephyr-Core-3.6.0/tests/drivers/hwinfo/api/src/ |
| D | main.c | 75 * @brief TestPurpose: verify get reset cause works.
79 * -# Read the reset cause
104 zassert_not_equal(cause, 0xDEADBEEF, "Reset cause not written."); in ZTEST()
111 * @brief TestPurpose: verify clear reset cause works. This may
112 * not work on some platforms, depending on how reset cause register
116 * -# Read the reset cause and store the result
117 * -# Call clear reset cause
118 * -# Read the reset cause again
121 * -# Reset cause value should change after calling clear reset cause.
158 "Reset cause did not change after clearing"); in ZTEST()
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| /Zephyr-Core-3.6.0/boards/arm/stm32f7508_dk/support/ |
| D | openocd.cfg | 5 reset halt
14 # Event reset-init already uses the maximum speed however adapter speed
15 # inherited from stm32f7x.cfg for reset-start defaults to 2000 kHz, so
17 $_TARGETNAME configure -event reset-start {
|
| /Zephyr-Core-3.6.0/dts/bindings/sensor/ |
| D | ti,ina230.yaml | 30 description: Diag alert register, default matches the power-on reset value
36 Default is the power-on reset value.
52 Default is the power-on reset value.
60 Default is the power-on reset value.
68 Default is the power-on reset value.
76 description: Mask register, default matches the power-on reset value
82 description: Alert register, default matches the power-on reset value
|
| /Zephyr-Core-3.6.0/drivers/bbram/ |
| D | Kconfig.stm32 | 15 powered-on by VBAT when the VDD power is switched off. They are not reset
16 by system reset or when the device wakes up from Standby mode. They are
17 reset by a backup domain reset.
|
