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/Zephyr-Core-3.5.0/dts/arm/rpi_pico/
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
18 die-temp0 = &die_temp;
22 #address-cells = <1>;
23 #size-cells = <0>;
26 compatible = "arm,cortex-m0+";
[all …]
/Zephyr-Core-3.5.0/tests/drivers/build_all/dac/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
37 #io-channel-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/reset/
Dst,stm32-rcc-rctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock Control (RCC) node.
6 This node is in charge of reset control for AHB (Advanced High Performance)
9 To specify the reset line in a peripheral, the standard resets property needs
19 RCC reset cells are available in
20 include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
22 compatible: "st,stm32-rcc-rctl"
24 include: [reset-controller.yaml, base.yaml]
27 "#reset-cells":
30 set-bit-to-deassert:
[all …]
Dgd,gd32-rctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the reset controller (RCTL).
9 To specify the reset line in a peripheral, the standard resets property needs
19 Predefined RCU reset cells are available in
20 include/zephyr/dts-bindings/reset/gd32{xxx}.h header files, where {xxx}
23 compatible: "gd,gd32-rctl"
25 include: [reset-controller.yaml, base.yaml]
28 "#reset-cells":
[all …]
Daspeed,ast10x0-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Aspeed AST10X0 Reset Controller
6 compatible: "aspeed,ast10x0-reset"
8 include: [base.yaml, reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
15 - id
Draspberrypi,pico-reset.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Raspberry Pi Pico Reset Controller
6 compatible: "raspberrypi,pico-reset"
8 include: [base.yaml, reset-controller.yaml]
13 reg-width:
15 description: The width of the reset registers in bytes. Default is 4 bytes.
16 active-low:
18 description: Set if reset is active low. Default is 0, which means active-high.
19 "#reset-cells":
[all …]
Dintel,socfpga-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Intel SoC FPGA Reset Controller
6 compatible: "intel,socfpga-reset"
8 include: [base.yaml, reset-controller.yaml]
13 active-low:
15 description: Add this property in dts node if the reset line is active_low, otherwise do not
17 "#reset-cells":
20 reset-cells:
21 - id
Dnuvoton,numaker-rst.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, Numaker-RESET
6 compatible: "nuvoton,numaker-rst"
8 include: [reset-controller.yaml, base.yaml]
14 "#reset-cells":
17 reset-cells:
18 - id
Dreset-controller.yaml1 # Copyright (c) 2022 Andrei-Edward Popa <andrei.popa105@yahoo.com>
2 # SPDX-License-Identifier: Apache-2.0
4 description: Reset Controller
7 "#reset-cells":
10 description: Number of cells in reset property
/Zephyr-Core-3.5.0/dts/bindings/test/
Dvnd,reset.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Test Reset Controller
6 compatible: "vnd,reset"
8 include: [base.yaml, reset-controller.yaml]
11 reg-width:
14 "#reset-cells":
17 reset-cells:
18 - id
/Zephyr-Core-3.5.0/dts/bindings/i2c/
Dti,tca954x-base.yaml2 # SPDX-License-Identifier: Apache-2.0
18 #address-cells = <1>;
19 #size-cells = <0>;
20 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
23 compatible: "ti,tca9546a-channel"
25 #address-cells = <1>;
26 #size-cells = <0>;
35 compatible: "ti,tca9546a-channel"
37 #address-cells = <1>;
38 #size-cells = <0>;
[all …]
/Zephyr-Core-3.5.0/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi2 * SPDX-License-Identifier: Apache-2.0
8 #include <arm64/armv8-a.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
15 #address-cells = <1>;
16 #size-cells= <0>;
20 compatible = "arm,cortex-a55";
21 enable-method = "psci";
27 compatible = "arm,cortex-a55";
28 enable-method = "psci";
[all …]
/Zephyr-Core-3.5.0/include/zephyr/devicetree/
Dreset.h3 * @brief Reset Controller Devicetree macro public API header file.
7 * Copyright (c) 2022, Andrei-Edward Popa
9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-reset-controller Devicetree Reset Controller API
27 * "resets" phandle-array property at an index
31 * reset1: reset-controller@... { ... };
33 * reset2: reset-controller@... { ... };
46 * @return the node identifier for the reset controller referenced at
56 * @return a node identifier for the reset controller at index 0
65 * resets phandle-array property by name
[all …]
/Zephyr-Core-3.5.0/tests/drivers/build_all/gpio/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
37 #gpio-cells = <2>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/dac/
Dgd,gd32-dac.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "gd,gd32-dac"
8 include: [dac-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
20 num-channels:
25 reset-val:
28 description: Reset value of DAC output. Defaults to 0, the SoC default.
30 "#io-channel-cells":
33 io-channel-cells:
34 - output
Dadi,ad56xx-base.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [dac-controller.yaml, spi-device.yaml]
7 "#io-channel-cells":
10 reset-gpios:
11 type: phandle-array
12 description: "GPIO for reset"
14 io-channel-cells:
15 - output
/Zephyr-Core-3.5.0/tests/drivers/build_all/video/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
42 reset-gpios = <&test_gpio 0 0>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f3x0/
Dgd32f3x0.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/gd32f3x0.h>
12 #include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f3x0.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(108)>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32l23x/
Dgd32l23x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/clock/gd32l23x-clocks.h>
12 #include <zephyr/dt-bindings/reset/gd32l23x.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m23";
22 clock-frequency = <DT_FREQ_M(64)>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/aspeed/
Dast10x0.dtsi2 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/ast10x0_clock.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
24 compatible = "mmio-sram";
32 compatible = "aspeed,ast10x0-clock";
33 #clock-cells = <1>;
37 compatible = "aspeed,ast10x0-reset";
[all …]
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dti,sn74hc595.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [gpio-controller.yaml, spi-device.yaml]
11 reset-gpios:
12 type: phandle-array
14 description: Reset pin
22 "#gpio-cells":
25 gpio-cells:
26 - pin
27 - flags
Drohm,bd8lb600fs.yaml4 # SPDX-License-Identifier: Apache-2.0
12 include: [gpio-controller.yaml, spi-device.yaml]
15 "#gpio-cells":
24 reset-gpios:
25 type: phandle-array
27 description: "GPIO for reset"
29 gpio-cells:
30 - pin
31 - flags
/Zephyr-Core-3.5.0/tests/drivers/build_all/ieee802154/boards/
Dnative_posix.overlay5 * SPDX-License-Identifier: Apache-2.0
10 #address-cells = <1>;
11 #size-cells = <1>;
15 gpio-controller;
17 #gpio-cells = <0x2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 clock-frequency = <2000000>;
30 cs-gpios = <&test_gpio 0 0>,
38 spi-max-frequency = <0>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/mfd/
Dnxp,sc18im704.yaml2 # SPDX-License-Identifier: Apache-2.0
15 pinctrl-0 = <&uart0_default>;
16 pinctrl-names = "default";
21 target-speed = <115200>;
22 reset-gpios = <&gpio1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
25 compatible = "nxp,sc18im704-i2c";
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "nxp,sc18im704-gpio";
34 gpio-controller;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dgd,gd32-cctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
19 Predefined RCU clock cells are available in
20 include/zephyr/dts-bindings/clock/gd32{xxx}-clocks.h header files, where {xxx}
23 compatible: "gd,gd32-cctl"
25 include: [clock-controller.yaml, base.yaml]
28 "#clock-cells":
31 clock-cells:
32 - id

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