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Searched full:rctl (Results 1 – 25 of 90) sorted by relevance

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/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi51 rctl: reset-controller { label
52 compatible = "gd,gd32-rctl";
77 resets = <&rctl GD32_RESET_USART0>;
86 resets = <&rctl GD32_RESET_USART1>;
95 resets = <&rctl GD32_RESET_USART2>;
104 resets = <&rctl GD32_RESET_UART3>;
113 resets = <&rctl GD32_RESET_UART4>;
122 resets = <&rctl GD32_RESET_USART5>;
131 resets = <&rctl GD32_RESET_UART6>;
140 resets = <&rctl GD32_RESET_UART7>;
[all …]
Dgd32f450.dtsi17 resets = <&rctl GD32_RESET_SPI3>;
28 resets = <&rctl GD32_RESET_SPI4>;
39 resets = <&rctl GD32_RESET_SPI5>;
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f403/
Dgd32f403.dtsi52 rctl: reset-controller { label
53 compatible = "gd,gd32-rctl";
79 resets = <&rctl GD32_RESET_USART0>;
88 resets = <&rctl GD32_RESET_USART1>;
97 resets = <&rctl GD32_RESET_USART2>;
106 resets = <&rctl GD32_RESET_UART3>;
115 resets = <&rctl GD32_RESET_UART4>;
124 resets = <&rctl GD32_RESET_SPI0>;
135 resets = <&rctl GD32_RESET_SPI1>;
146 resets = <&rctl GD32_RESET_SPI2>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32e10x/
Dgd32e10x.dtsi45 rctl: reset-controller { label
46 compatible = "gd,gd32-rctl";
71 resets = <&rctl GD32_RESET_USART0>;
80 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_USART2>;
98 resets = <&rctl GD32_RESET_UART3>;
107 resets = <&rctl GD32_RESET_UART4>;
115 resets = <&rctl GD32_RESET_DAC>;
130 resets = <&rctl GD32_RESET_I2C0>;
143 resets = <&rctl GD32_RESET_I2C1>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32e50x/
Dgd32e50x.dtsi45 rctl: reset-controller { label
46 compatible = "gd,gd32-rctl";
85 resets = <&rctl GD32_RESET_USART0>;
94 resets = <&rctl GD32_RESET_USART1>;
103 resets = <&rctl GD32_RESET_USART2>;
112 resets = <&rctl GD32_RESET_UART3>;
121 resets = <&rctl GD32_RESET_UART4>;
131 resets = <&rctl GD32_RESET_USART5>;
139 resets = <&rctl GD32_RESET_DAC>;
154 resets = <&rctl GD32_RESET_I2C0>;
[all …]
Dgd32e507xe.dtsi18 resets = <&rctl GD32_RESET_TIMER7>;
36 resets = <&rctl GD32_RESET_TIMER8>;
53 resets = <&rctl GD32_RESET_TIMER9>;
70 resets = <&rctl GD32_RESET_TIMER10>;
87 resets = <&rctl GD32_RESET_TIMER11>;
104 resets = <&rctl GD32_RESET_TIMER12>;
121 resets = <&rctl GD32_RESET_TIMER13>;
/Zephyr-Core-3.5.0/dts/riscv/gigadevice/
Dgd32vf103.dtsi73 rctl: reset-controller { label
74 compatible = "gd,gd32-rctl";
99 resets = <&rctl GD32_RESET_USART0>;
108 resets = <&rctl GD32_RESET_USART1>;
117 resets = <&rctl GD32_RESET_USART2>;
126 resets = <&rctl GD32_RESET_UART3>;
135 resets = <&rctl GD32_RESET_UART4>;
144 resets = <&rctl GD32_RESET_ADC0>;
155 resets = <&rctl GD32_RESET_ADC1>;
165 resets = <&rctl GD32_RESET_DAC>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32a50x/
Dgd32a50x.dtsi52 rctl: reset-controller { label
53 compatible = "gd,gd32-rctl";
80 resets = <&rctl GD32_RESET_USART0>;
89 resets = <&rctl GD32_RESET_USART1>;
98 resets = <&rctl GD32_RESET_USART2>;
106 resets = <&rctl GD32_RESET_DAC>;
121 resets = <&rctl GD32_RESET_I2C0>;
134 resets = <&rctl GD32_RESET_I2C1>;
143 resets = <&rctl GD32_RESET_SPI0>;
154 resets = <&rctl GD32_RESET_SPI1>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f3x0/
Dgd32f3x0.dtsi43 rctl: reset-controller { label
44 compatible = "gd,gd32-rctl";
70 resets = <&rctl GD32_RESET_USART0>;
79 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_ADC>;
115 resets = <&rctl GD32_RESET_WWDGT>;
133 resets = <&rctl GD32_RESET_GPIOA>;
143 resets = <&rctl GD32_RESET_GPIOB>;
153 resets = <&rctl GD32_RESET_GPIOC>;
163 resets = <&rctl GD32_RESET_GPIOD>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32l23x/
Dgd32l23x.dtsi43 rctl: reset-controller { label
44 compatible = "gd,gd32-rctl";
74 resets = <&rctl GD32_RESET_USART0>;
83 resets = <&rctl GD32_RESET_USART1>;
92 resets = <&rctl GD32_RESET_UART3>;
101 resets = <&rctl GD32_RESET_ADC>;
133 resets = <&rctl GD32_RESET_GPIOA>;
143 resets = <&rctl GD32_RESET_GPIOB>;
153 resets = <&rctl GD32_RESET_GPIOC>;
163 resets = <&rctl GD32_RESET_GPIOD>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/reset/
Dgd,gd32-rctl.yaml6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the reset controller (RCTL).
15 resets = <&rctl GD32_RESET_GPIOA>;
23 compatible: "gd,gd32-rctl"
/Zephyr-Core-3.5.0/dts/arm/st/f4/
Dstm32f413.dtsi17 resets = <&rctl STM32_RESET(APB1, 19U)>;
26 resets = <&rctl STM32_RESET(APB1, 20U)>;
35 resets = <&rctl STM32_RESET(APB1, 30U)>;
44 resets = <&rctl STM32_RESET(APB1, 31U)>;
53 resets = <&rctl STM32_RESET(APB2, 6U)>;
62 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f405.dtsi50 resets = <&rctl STM32_RESET(APB1, 18U)>;
59 resets = <&rctl STM32_RESET(APB1, 19U)>;
68 resets = <&rctl STM32_RESET(APB1, 20U)>;
77 resets = <&rctl STM32_RESET(APB1, 4U)>;
93 resets = <&rctl STM32_RESET(APB1, 5U)>;
109 resets = <&rctl STM32_RESET(APB2, 1U)>;
132 resets = <&rctl STM32_RESET(APB1, 6U)>;
154 resets = <&rctl STM32_RESET(APB1, 7U)>;
176 resets = <&rctl STM32_RESET(APB1, 8U)>;
/Zephyr-Core-3.5.0/dts/arm/st/f0/
Dstm32f030Xc.dtsi33 resets = <&rctl STM32_RESET(APB1, 18U)>;
42 resets = <&rctl STM32_RESET(APB1, 19U)>;
51 resets = <&rctl STM32_RESET(APB1, 20U)>;
60 resets = <&rctl STM32_RESET(APB2, 5U)>;
69 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f091.dtsi23 resets = <&rctl STM32_RESET(APB1, 20U)>;
32 resets = <&rctl STM32_RESET(APB2, 5U)>;
41 resets = <&rctl STM32_RESET(APB2, 6U)>;
50 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f070Xb.dtsi32 resets = <&rctl STM32_RESET(APB1, 18U)>;
41 resets = <&rctl STM32_RESET(APB1, 19U)>;
72 resets = <&rctl STM32_RESET(APB1, 4U)>;
83 resets = <&rctl STM32_RESET(APB1, 5U)>;
/Zephyr-Core-3.5.0/dts/arm/st/l0/
Dstm32l071.dtsi61 resets = <&rctl STM32_RESET(APB1, 1U)>;
83 resets = <&rctl STM32_RESET(APB1, 4U)>;
99 resets = <&rctl STM32_RESET(APB1, 5U)>;
115 resets = <&rctl STM32_RESET(APB2, 5U)>;
137 resets = <&rctl STM32_RESET(APB2, 14U)>;
146 resets = <&rctl STM32_RESET(APB1, 19U)>;
155 resets = <&rctl STM32_RESET(APB1, 20U)>;
/Zephyr-Core-3.5.0/dts/arm/st/f1/
Dstm32f103Xg.dtsi36 resets = <&rctl STM32_RESET(APB2, 19U)>;
53 resets = <&rctl STM32_RESET(APB2, 20U)>;
70 resets = <&rctl STM32_RESET(APB2, 21U)>;
87 resets = <&rctl STM32_RESET(APB1, 6U)>;
104 resets = <&rctl STM32_RESET(APB1, 7U)>;
121 resets = <&rctl STM32_RESET(APB1, 8U)>;
Dstm32f103Xc.dtsi30 resets = <&rctl STM32_RESET(APB1, 19U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
48 resets = <&rctl STM32_RESET(APB1, 3U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
76 resets = <&rctl STM32_RESET(APB1, 5U)>;
144 resets = <&rctl STM32_RESET(APB2, 13U)>;
/Zephyr-Core-3.5.0/dts/arm/st/l4/
Dstm32l471.dtsi52 resets = <&rctl STM32_RESET(APB1L, 18U)>;
61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
111 resets = <&rctl STM32_RESET(APB1L, 1U)>;
133 resets = <&rctl STM32_RESET(APB1L, 2U)>;
155 resets = <&rctl STM32_RESET(APB1L, 3U)>;
177 resets = <&rctl STM32_RESET(APB1L, 5U)>;
193 resets = <&rctl STM32_RESET(APB2, 13U)>;
210 resets = <&rctl STM32_RESET(APB2, 18U)>;
243 resets = <&rctl STM32_RESET(APB2, 10U)>;
/Zephyr-Core-3.5.0/dts/arm/st/f2/
Dstm32f2.dtsi99 rctl: reset-controller { label
100 compatible = "st,stm32-rcc-rctl";
232 resets = <&rctl STM32_RESET(APB2, 4U)>;
241 resets = <&rctl STM32_RESET(APB1, 17U)>;
250 resets = <&rctl STM32_RESET(APB1, 18U)>;
259 resets = <&rctl STM32_RESET(APB2, 5U)>;
268 resets = <&rctl STM32_RESET(APB1, 19U)>;
277 resets = <&rctl STM32_RESET(APB1, 20U)>;
409 resets = <&rctl STM32_RESET(APB2, 0U)>;
426 resets = <&rctl STM32_RESET(APB1, 0U)>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/g0/
Dstm32g070.dtsi18 resets = <&rctl STM32_RESET(APB1L, 18U)>;
27 resets = <&rctl STM32_RESET(APB1L, 19U)>;
36 resets = <&rctl STM32_RESET(APB1H, 16U)>;
/Zephyr-Core-3.5.0/dts/arm/st/f3/
Dstm32f373.dtsi72 resets = <&rctl STM32_RESET(APB1, 2U)>;
89 resets = <&rctl STM32_RESET(APB1, 3U)>;
106 resets = <&rctl STM32_RESET(APB1, 6U)>;
123 resets = <&rctl STM32_RESET(APB1, 7U)>;
140 resets = <&rctl STM32_RESET(APB1, 8U)>;
157 resets = <&rctl STM32_RESET(APB1, 9U)>;
174 resets = <&rctl STM32_RESET(APB2, 19U)>;
/Zephyr-Core-3.5.0/dts/arm/st/h5/
Dstm32h562.dtsi61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
79 resets = <&rctl STM32_RESET(APB1H, 0U)>;
88 resets = <&rctl STM32_RESET(APB1L, 26U)>;
97 resets = <&rctl STM32_RESET(APB1H, 1U)>;
188 resets = <&rctl STM32_RESET(APB1L, 2U)>;
209 resets = <&rctl STM32_RESET(APB1L, 3U)>;
230 resets = <&rctl STM32_RESET(APB1L, 6U)>;
251 resets = <&rctl STM32_RESET(APB1L, 7U)>;
272 resets = <&rctl STM32_RESET(APB1L, 8U)>;
/Zephyr-Core-3.5.0/dts/arm/st/f7/
Dstm32f7.dtsi128 rctl: reset-controller { label
129 compatible = "st,stm32-rcc-rctl";
246 resets = <&rctl STM32_RESET(APB2, 4U)>;
255 resets = <&rctl STM32_RESET(APB1, 17U)>;
264 resets = <&rctl STM32_RESET(APB1, 18U)>;
273 resets = <&rctl STM32_RESET(APB1, 19U)>;
282 resets = <&rctl STM32_RESET(APB1, 20U)>;
291 resets = <&rctl STM32_RESET(APB2, 5U)>;
300 resets = <&rctl STM32_RESET(APB1, 30U)>;
309 resets = <&rctl STM32_RESET(APB1, 31U)>;
[all …]

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