| /Zephyr-Core-3.6.0/soc/sparc/leon3/ |
| D | linker.ld | 19 RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
24 REGION_ALIAS("REGION_TEXT", RAM);
25 REGION_ALIAS("REGION_RODATA", RAM);
26 REGION_ALIAS("REGION_DATA_VMA", RAM);
27 REGION_ALIAS("REGION_DATA_LMA", RAM);
28 REGION_ALIAS("REGION_BSS", RAM);
30 #define ROMABLE_REGION RAM
31 #define RAMABLE_REGION RAM
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| /Zephyr-Core-3.6.0/dts/bindings/memory-controllers/ |
| D | nxp,flexram.yaml | 4 description: NXP FlexRAM on-chip ram controller
22 on arbitrary address access in any on chip RAM region.
24 flexram,num-ram-banks:
28 Number of RAM banks in the SOC ram array
34 Size of each RAM bank in KB
39 Custom mapping of runtime RAM bank partitions. If this
47 TCM RAM read will finish in 2 cycles instead of 1.
52 TCM RAM write will finish in 2 cycles instead of 1.
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| /Zephyr-Core-3.6.0/soc/sparc/gr716a/ |
| D | linker.ld | 18 * available on all systems. bootprom, RAM and SRAM are always available.
26 RAM (rw) : ORIGIN = 0x30000000, LENGTH = 64K
34 REGION_ALIAS("REGION_RODATA", RAM);
35 REGION_ALIAS("REGION_DATA_VMA", RAM);
36 REGION_ALIAS("REGION_DATA_LMA", RAM);
37 REGION_ALIAS("REGION_BSS", RAM);
39 #define ROMABLE_REGION RAM
40 #define RAMABLE_REGION RAM
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| /Zephyr-Core-3.6.0/samples/net/zperf/ |
| D | Kconfig | 7 bool "Relocate networking code into RAM"
10 Relocate networking code into RAM when running the zperf
12 RAM.
17 string "Networking code RAM location"
18 default "RAM"
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| /Zephyr-Core-3.6.0/include/zephyr/display/ |
| D | ssd16xx.h | 13 * SSD16xx RAM type for direct RAM access
16 /** The black RAM buffer. This is typically the buffer used to
21 /* The red RAM buffer. This is typically the old frame buffer
30 * RAM.
33 * @param ram_type Type of RAM to read from
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| /Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 17 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
23 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
30 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
36 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
43 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
50 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
57 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
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| /Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 16 bool "Support for external, SPI-connected RAM"
18 This enables support for an external SPI RAM chip, connected in
22 int "Minimum threshold for external RAM allocation"
29 memory will be allocated from internal RAM.
48 menu "SPI RAM config"
52 prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
61 prompt "Type of SPI RAM chip in use"
87 prompt "Set RAM clock speed"
90 Select the speed for the SPI RAM chip.
91 If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/disk/ |
| D | zephyr,ram-disk.yaml | 4 description: RAM disk
6 compatible: "zephyr,ram-disk"
30 ram-region:
33 Optional phandle to the memory region to be used as a RAM disk,
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| /Zephyr-Core-3.6.0/include/zephyr/arch/mips/ |
| D | linker.ld | 18 #define ROMABLE_REGION RAM
19 #define RAMABLE_REGION RAM
27 RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
32 REGION_ALIAS("REGION_TEXT", RAM);
33 REGION_ALIAS("REGION_RODATA", RAM);
34 REGION_ALIAS("REGION_DATA_VMA", RAM);
35 REGION_ALIAS("REGION_DATA_LMA", RAM);
36 REGION_ALIAS("REGION_BSS", RAM);
129 #include <zephyr/linker/common-ram.ld>
134 #include <snippets-ram-sections.ld>
[all …]
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| /Zephyr-Core-3.6.0/include/zephyr/drivers/flash/ |
| D | flash_simulator.h | 21 * @brief Obtain a pointer to the RAM buffer used but by the simulator
23 * This function allows the caller to get the address and size of the RAM buffer
27 * @param[out] mock_size size of the ram buffer.
29 * @retval pointer to the ram buffer
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| /Zephyr-Core-3.6.0/drivers/flash/ |
| D | Kconfig.mcux | 87 bool "MCUX FlexSPI NOR write RAM buffer"
91 Copy the data to a RAM buffer before writing it to the flash.
96 bool "MCUX FlexSPI HYPERFLASH write RAM buffer"
100 Copy the data to a RAM buffer before writing it to the flash.
118 bool "RAM"
126 default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
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| /Zephyr-Core-3.6.0/samples/boards/nrf/system_off/src/ |
| D | retained.c | 19 /* nRF52 RAM (really, RAM AHB slaves) are partitioned as:
28 /* Inclusive address of RAM start */
31 /* Exclusive address of RAM end */
34 /* Size of a controllable RAM section in the small blocks */
37 /* Number of controllable RAM sections in each of the lower blocks */
49 /* Inclusive address of the RAM range covered by large sections */
52 /* Size of a controllable RAM section in large blocks */
55 /* Set or clear RAM retention in SYSTEM_OFF for the provided object.
84 * corresponding RAM OFF retention bit in the parent block. in ram_range_retain()
98 /* RAM[x] supports only 16 sections, each its own bit in ram_range_retain()
|
| /Zephyr-Core-3.6.0/subsys/demand_paging/backing_store/ |
| D | Kconfig | 16 bool "RAM-based test backing store"
18 This implements a backing store using physical RAM pages that the
35 int "Number of pages for RAM backing store"
38 Number of pages of backing store memory to reserve in RAM. All test
|
| /Zephyr-Core-3.6.0/include/zephyr/drivers/can/ |
| D | can_mcan.h | 59 /* RAM Watchdog register */
428 * @brief Get the Bosch M_CAN Message RAM offset
431 * @return the Message RAM offset in bytes
437 * @brief Get the number of standard (11-bit) filter elements in Bosch M_CAN Message RAM
446 * @brief Get the number of extended (29-bit) filter elements in Bosch M_CAN Message RAM
455 * @brief Get the number of Rx FIFO 0 elements in Bosch M_CAN Message RAM
464 * @brief Get the number of Rx FIFO 1 elements in Bosch M_CAN Message RAM
473 * @brief Get the number of Rx Buffer elements in Bosch M_CAN Message RAM
482 * @brief Get the number of Tx Event FIFO elements in Bosch M_CAN Message RAM
491 * @brief Get the number of Tx Buffer elements in Bosch M_CAN Message RAM
[all …]
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| /Zephyr-Core-3.6.0/tests/subsys/fs/fat_fs_dual_drive/ |
| D | app.overlay | 9 compatible = "zephyr,ram-disk";
10 disk-name = "RAM";
16 compatible = "zephyr,ram-disk";
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| /Zephyr-Core-3.6.0/include/zephyr/arch/nios2/ |
| D | linker.ld | 31 * _RAM_ADDR Beginning of RAM
32 * _RAM_SIZE Size of RAM in bytes
36 * 1. Non-XIP systems where the reset vector is at the beginning of RAM
39 * the exception vector is in RAM
51 #define ROMABLE_REGION RAM
53 #define RAMABLE_REGION RAM
63 RAM (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)
74 RAM (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)
172 /* Altera strongly recommends keeping exception entry code in RAM
193 #include <zephyr/linker/common-ram.ld>
[all …]
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| /Zephyr-Core-3.6.0/include/zephyr/arch/x86/ |
| D | memory.ld | 12 * are in RAM.
17 * in RAM and are copied from flash at boot. Text/rodata linked in-place in
34 /* Bounds of physical RAM from DTS */
39 * the same as its physical location, although an identity mapping for RAM
51 /* "kernel RAM" for linker VMA allocations starts at the offset */
67 /* Physical RAM location where the kernel image is loaded */
87 * or copied into physical RAM by a loader (MMU)
97 RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
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| /Zephyr-Core-3.6.0/kernel/ |
| D | Kconfig.vm | 23 address from DTS, in which case RAM will be identity-mapped. Some
24 architectures may require RAM to be mapped in this way; they may have
25 just one RAM region and doing this makes linking much simpler, as
26 at least when the kernel boots all virtual RAM addresses are the same
30 Otherwise, if RAM isn't identity-mapped:
35 the kernel's address space, such as not overlapping physical RAM
36 regions if RAM is not identity-mapped, or the virtual and physical
50 if this is not the same offset from the beginning of RAM.
74 for mapping driver MMIO regions, as well as special RAM mapping use-cases
81 RAM size larger than the defined bounds of the virtual address space.
|
| /Zephyr-Core-3.6.0/samples/boards/stm32/power_mgmt/suspend_to_ram/ |
| D | README.rst | 1 .. _stm32-pm-suspend-to-ram-sample:
3 STM32 PM Suspend to RAM
13 .. _stm32-pm-suspend-to-ram-sample-requirements:
22 for LPTIM (which is disabled). The board shall also have RAM retention to be
|
| /Zephyr-Core-3.6.0/dts/arm/st/h7/ |
| D | stm32h745.dtsi | 54 ram-size = <4096>;
68 ram-size = <4096>;
85 * The RAM memories placed here can be used by both cores M4/M7
90 /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
96 /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
103 /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
110 /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
117 /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
|
| /Zephyr-Core-3.6.0/soc/riscv/ite_ec/it8xxx2/ |
| D | ilm.c | 20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
22 * *must* be in the Flash memory space: it is not permitted to execute from RAM addresses, only
23 * through ILM mappings into RAM.
25 * When a RAM block is configured as ILM, accesses to addresses matching the corresponding Scratch
26 * SRAM address register (SCARn{H,M,L}) are redirected to the corresponding ILM block in RAM.
29 * 0x80100000..0x80101000 (the first 4k block of RAM).
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
88 return -EFAULT; /* Past the end of RAM */ in it8xxx2_configure_ilm_block()
106 /* Ensure scratch RAM for block data access is enabled */ in it8xxx2_configure_ilm_block()
[all …]
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| /Zephyr-Core-3.6.0/drivers/bbram/ |
| D | Kconfig | 5 bool "Battery-backed RAM (BBRAM) drivers"
7 Enable BBRAM (battery-backed RAM) driver configuration.
16 bool "Battery-backed RAM shell"
|
| /Zephyr-Core-3.6.0/samples/subsys/fs/format/ |
| D | README.rst | 14 * FAT file system on RAM disk
22 The RAM disk scenario is supported on the mimxrt1064_evk board.
23 To build the RAM disk sample, the configuration `prj_ram.conf` needs to be used by setting `CONF_FI…
33 The RAM disk sample for the MIMXRT1064-EVK board can be build as follow:
|
| /Zephyr-Core-3.6.0/include/zephyr/arch/x86/intel64/ |
| D | linker.ld | 9 #define ROMABLE_REGION RAM
10 #define RAMABLE_REGION RAM
16 * the kernel is just one blob with the same RWX permissions on all RAM
29 * The "locore" must be in the 64K of RAM, so that 16-bit code (with
152 #include <snippets-ram-sections.ld>
184 #include <zephyr/linker/common-ram.ld>
185 #include <zephyr/linker/cplusplus-ram.ld>
193 /* Must be last in RAM */
198 #include <zephyr/linker/ram-end.ld>
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| /Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/xc7zxxxs/ |
| D | Kconfig.soc | 17 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
23 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
30 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
|
