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/hal_rpi_pico-latest/src/rp2_common/pico_double/
Ddouble_aeabi_rp2040.S63 push {r0, r2}
85 push {r3, r4}
99 push {r3, r4}
123 push {r4-r7}
161 push {r0-r3, lr}
176 push {r0-r3, lr}
191 push {r4, lr}
243 push {r0-r3, lr}
274 push {r0-r7,r14}
291 push {r0-r7,r14}
[all …]
Ddouble_v1_rom_shim_rp2040.S22 push {r0-r2, lr}
71 push {r0-r3}
72 push {r14}
73 push {r0-r3}
159 push {r0-r3}
165 push {r4-r7,r14}
174 push {r4-r7,r14}
470 push {r4-r7,r14}
476 push {r0-r2,r4,r7}
623 push {r4-r7,r14}
[all …]
Ddouble_conv_m33.S67 @ push {r14}
134 @ push {r14}
188 @ push {r14}
231 @ push {r14}
265 @ push {r14}
Ddouble_sci_m33.S102 push {r14}
150 push {r12}
210 push {r6,r7} @ packed cos θ
279 push {r6,r7}
284 push {r2-r5, lr}
315 push {r4-r10,r14}
404 push {r2-r7}
410 push {r0,r1}
430 push {r2-r7}
436 push {r0,r1}
[all …]
Ddouble_aeabi_dcp.S41 push {lr} // 16-bit instruction
59 push {r0, r1}
103 push {r4,r14}
/hal_rpi_pico-latest/src/rp2_common/pico_float/
Dfloat_aeabi_rp2040.S131 push {r0, r1, lr}
144 push {r0, r1, lr}
157 push {r4, lr}
204 push {r0, r1, lr}
232 push {r0-r2, lr}
244 push {r0-r2, lr}
293 push {lr}
306 push {lr}
315 push {lr}
328 push {lr}
[all …]
Dfloat_v1_rom_shim_rp2040.S28 push {r0-r2, lr}
67 push {r4,r5,r14}
82 push {r4,r5,r14}
113 push {r4,r5,r14}
207 push {r14}
223 push {r4,r14}
Dfloat_conv_m33.S60 @ push {r14}
113 @ push {r14}
149 @ push {r14}
161 @ push {r14}
216 @ push {r14}
Dfloat_sci_m33.S248 push {r14}
394 push {r4-r6,r14}
563 push {r14}
600 push {r12}
665 push {r3}
670 push {r1, r2, lr}
699 push {r4-r6,r14}
782 push {r0}
Dfloat_aeabi_dcp.S41 push {lr} // 16-bit instruction
59 push {r0, r1}
/hal_rpi_pico-latest/src/rp2_common/pico_bit_ops/
Dbit_ops_aeabi.S75 push {lr}
91 push {lr}
101 push {r1, r3, lr}
121 push {lr}
124 push {r1, r3}
/hal_rpi_pico-latest/src/rp2_common/pico_divider/
Ddivider_hardware.S55 push {r4, r5, r6, r7, lr}
134 push {r2, lr}
196 push {r2, lr}
238 push {r4, lr}
266 push {r4, lr}
292 push {r14}
315 push {r14}
325 push {r14}
368 push {r14}
399 push {r7}
[all …]
/hal_rpi_pico-latest/src/rp2_common/hardware_divider/include/hardware/
Ddivider_helper.S24 // originally we did this, however a) it uses r3, and b) the push and dividend/divisor
34 // 6 cycle push + 2 ldr ensures the 8 cycle delay before remainder and quotient are ready
35 push {r4, r5, r6, r7, lr} label
/hal_rpi_pico-latest/src/rp2_common/hardware_pio/include/hardware/
Dpio_instructions.h335 /*! \brief Encode a PUSH instruction
338 * This is the equivalent of `PUSH <if_full>, <block>`
340 * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...`
341 * \param block true for `PUSH ... BLOCK`, false for `PUSH ...`
/hal_rpi_pico-latest/src/rp2_common/pico_multicore/include/pico/
Dmulticore.h160 /*! \brief Push data on to the write FIFO (data to the other core).
169 * \param data A 32 bit value to push on to the FIFO
173 /*! \brief Push data on to the write FIFO (data to the other core).
182 * \param data A 32 bit value to push on to the FIFO
195 /*! \brief Push data on to the write FIFO (data to the other core) with timeout.
201 * \param data A 32 bit value to push on to the FIFO
/hal_rpi_pico-latest/test/pico_float_test/llvm/
Dcall_apsr.S25 push {lr}
34 push {r4, lr}
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/
Dcmsis_armcc.h573 …#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(p…
586 …#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(p…
599 …#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(…
614 …#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) …
629 …#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) …
644 …#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) …
/hal_rpi_pico-latest/src/rp2350/hardware_regs/include/hardware/regs/
Dxip_aux.h35 // Description : Inhibit the RX FIFO push that would correspond to this TX FIFO
94 // push this to the DIRECT_RX FIFO.
113 // RX FIFO push will also contain 16 bits of data. The least-
/hal_rpi_pico-latest/src/rp2_common/hardware_irq/
Dirq_handler_chain.S67 push {r0, lr} // Save EXC_RETURN token, so `pop {r0, pc}` will return from interrupt
75 .insn 0xb842 // cm.push {ra}, -16: Save ultimate return address
/hal_rpi_pico-latest/src/rp2040/boot_stage2/
Dboot2_is25lp080.S94 push {lr}
206 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
208 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_at25sf128a.S101 push {lr}
230 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
232 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_w25q080.S101 push {lr}
232 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
234 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
/hal_rpi_pico-latest/src/rp2350/boot_stage2/
Dboot2_at25sf128a.S97 push {lr}
226 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
228 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_is25lp080.S90 push {lr}
202 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
204 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_w25x10cl.S82 push {lr}
135 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
137 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction

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