Searched +full:psoc6 +full:- +full:intmux (Results 1 – 3 of 3) sorted by relevance
4 * SPDX-License-Identifier: Apache-2.07 #include <arm/armv6-m.dtsi>8 #include <infineon/cat1a/legacy/psoc6.dtsi>13 compatible = "arm,cortex-m0+";16 /delete-node/ cpu@1;20 intmux: intmux@40210020 { label21 /* see cypress,psoc6-int-mux.yaml */22 compatible = "cypress,psoc6-intmux";26 #address-cells = <1>;27 #size-cells = <1>;[all …]
3 # SPDX-License-Identifier: Apache-2.08 see cypress,psoc6-intmux10 compatible: "cypress,psoc6-intmux-ch"12 include: [interrupt-controller.yaml, base.yaml]21 interrupt-cells:22 - irq23 - priority
3 # SPDX-License-Identifier: Apache-2.08 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that10 to be processed in the Cortex-M0+ CPU.12 At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to14 4 interrupt sources by grouping intmux channels. These means that each byte15 from intmux[0~7] store a 'vector number' which selects the peripheral17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources21 configuration and how the Cortex-M0+ NVIC sources are organized. Each22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.[all …]
