| /trusted-firmware-m-latest/secure_fw/spm/core/ |
| D | thread.h | 27 /* Priorities. Lower value has higher priority */
46 uint8_t priority; /* Priority */ member
69 * priority - Initial priority
72 (p_thrd)->priority = (uint8_t)(prio); \
79 * Set thread priority.
83 * priority - Priority value (0~255)
86 * The new priority may not take effect immediately.
88 #define THRD_SET_PRIORITY(p_thrd, priority) \ argument
89 p_thrd->priority = (uint8_t)(priority)
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| D | thread.c | 45 * First runnable thread has highest priority since threads are in thrd_next()
46 * sorted by priority. in thrd_next()
70 if (*head == NULL || (node->priority <= (*head)->priority)) { in insert_by_prior()
76 while (iter->next && (node->priority > iter->next->priority)) { in insert_by_prior()
89 /* Insert a new thread with priority */ in thrd_start()
110 ((RNBL_HEAD == NULL) || (p_thrd->priority < RNBL_HEAD->priority))) { in thrd_set_state()
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| /trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Include/a-profile/ |
| D | irq_ctrl.h | 87 /* Interrupt priority bit-masks */
88 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value…
89 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority …
160 /// Set interrupt priority value.
162 /// \param[in] priority interrupt priority value
164 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
166 /// Get interrupt priority.
168 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
171 /// Set priority masking threshold.
172 /// \param[in] priority priority masking threshold value
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| /trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/RTOS2/Include/ |
| D | cmsis_os2.h | 123 /// Priority values.
125 osPriorityNone = 0, ///< No priority (not initialized).
127 osPriorityLow = 8, ///< Priority: low
128 osPriorityLow1 = 8+1, ///< Priority: low + 1
129 osPriorityLow2 = 8+2, ///< Priority: low + 2
130 osPriorityLow3 = 8+3, ///< Priority: low + 3
131 osPriorityLow4 = 8+4, ///< Priority: low + 4
132 osPriorityLow5 = 8+5, ///< Priority: low + 5
133 osPriorityLow6 = 8+6, ///< Priority: low + 6
134 osPriorityLow7 = 8+7, ///< Priority: low + 7
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32l5xx/hal/Src/ |
| D | stm32l5xx_hal_cortex.c | 23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
24 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
28 The pending IRQ priority will be managed only by the sub priority.
30 -@- IRQ priority order (sorted by highest to lowest priority):
31 (+@) Lowest pre-emption priority
32 (+@) Lowest sub priority
33 (+@) Lowest hardware priority (IRQ number)
44 (++) Configures the SysTick IRQ priority to the lowest value (0x07).
55 (+) You can change the SysTick IRQ priority by calling the
68 The table below gives the allowed values of the pre-emption priority and subpriority according
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/hal/Src/ |
| D | stm32u5xx_hal_cortex.c | 35 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
36 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
40 The pending IRQ priority will be managed only by the sub priority.
42 -@- IRQ priority order (sorted by highest to lowest priority):
43 (+@) Lowest pre-emption priority
44 (+@) Lowest sub priority
45 (+@) Lowest hardware priority (IRQ number)
56 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
67 (+) You can change the SysTick IRQ priority by calling the
95 The table below gives the allowed values of the pre-emption priority and subpriority according
[all …]
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| /trusted-firmware-m-latest/platform/ext/target/stm/stm32l562e_dk/include/ |
| D | stm32l562e_discovery_conf.h | 37 /* Button interrupt priority */
38 #define BSP_BUTTON_USER_IT_PRIORITY 0x07UL /* Default is lowest priority level */
40 /* IDD interrupt priority */
41 #define BSP_IDD_IT_PRIORITY 0x07UL /* Default is lowest priority level */
43 /* TS interrupt priority */
44 #define BSP_TS_IT_PRIORITY 0x07UL /* Default is lowest priority level */
47 #define BSP_AUDIO_OUT_IT_PRIORITY 0x07UL /* Default is lowest priority level */
48 #define BSP_AUDIO_IN_IT_PRIORITY 0x07UL /* Default is lowest priority level */
50 /* SD card interrupt priority */
51 #define BSP_SD_IT_PRIORITY 0x07UL /* Default is lowest priority level */
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/hal/Src/ |
| D | stm32h5xx_hal_cortex.c | 34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
35 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
39 The pending IRQ priority will be managed only by the sub priority.
41 -@- IRQ priority order (sorted by highest to lowest priority):
42 (+@) Lowest pre-emption priority
43 (+@) Lowest sub priority
44 (+@) Lowest hardware priority (IRQ number)
55 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
66 (+) You can change the SysTick IRQ priority by calling the
94 The table below gives the allowed values of the pre-emption priority and subpriority according
[all …]
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| /trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Source/ |
| D | irq_ctrl_gic.c | 274 /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ in IRQ_GetActiveIRQ()
363 /// Set interrupt priority value.
364 __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { in IRQ_SetPriority() argument
368 GIC_SetPriority ((IRQn_Type)irqn, priority); in IRQ_SetPriority()
378 /// Get interrupt priority.
380 uint32_t priority; in IRQ_GetPriority() local
383 priority = GIC_GetPriority ((IRQn_Type)irqn); in IRQ_GetPriority()
385 priority = IRQ_PRIORITY_ERROR; in IRQ_GetPriority()
388 return (priority); in IRQ_GetPriority()
392 /// Set priority masking threshold.
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| /trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Include/ |
| D | core_cm0.h | 326 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
351 …__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Register…
734 \brief Set Interrupt Priority
735 \details Sets the priority of a device specific interrupt or a processor exception.
739 \param [in] priority Priority to set.
740 \note The priority cannot be set for every processor exception.
742 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) in __NVIC_SetPriority() argument
747 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
752 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
758 \brief Get Interrupt Priority
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| D | core_cm1.h | 326 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
351 …__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Register…
761 \brief Set Interrupt Priority
762 \details Sets the priority of a device specific interrupt or a processor exception.
766 \param [in] priority Priority to set.
767 \note The priority cannot be set for every processor exception.
769 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) in __NVIC_SetPriority() argument
774 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
779 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
785 \brief Get Interrupt Priority
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| D | core_cm0plus.h | 340 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
369 …__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Register…
852 \brief Set Interrupt Priority
853 \details Sets the priority of a device specific interrupt or a processor exception.
857 \param [in] priority Priority to set.
858 \note The priority cannot be set for every processor exception.
860 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) in __NVIC_SetPriority() argument
865 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
870 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
876 \brief Get Interrupt Priority
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| D | core_cm3.h | 358 …__IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
388 …__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Register…
1472 \brief Set Priority Grouping
1473 \details Sets the priority grouping field using the required unlock sequence.
1476 In case of a conflict between priority grouping and available
1477 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1478 \param [in] PriorityGroup Priority grouping field.
1489 …orityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ in __NVIC_SetPriorityGrouping()
1495 \brief Get Priority Grouping
1496 \details Reads the priority grouping field from the NVIC Interrupt Controller.
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| D | core_sc300.h | 358 …__IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
388 …__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Register…
1455 \brief Set Priority Grouping
1456 \details Sets the priority grouping field using the required unlock sequence.
1459 In case of a conflict between priority grouping and available
1460 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1461 \param [in] PriorityGroup Priority grouping field.
1472 …orityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ in __NVIC_SetPriorityGrouping()
1478 \brief Get Priority Grouping
1479 \details Reads the priority grouping field from the NVIC Interrupt Controller.
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| D | core_cm23.h | 366 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
395 …__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Register…
1560 \brief Set Interrupt Priority
1561 \details Sets the priority of a device specific interrupt or a processor exception.
1565 \param [in] priority Priority to set.
1566 \note The priority cannot be set for every processor exception.
1568 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) in __NVIC_SetPriority() argument
1573 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
1578 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
1584 \brief Get Interrupt Priority
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| /trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/host/src/tests/TestAL/pal/include/ |
| D | test_pal_thread.h | 38 * @brief This function returns the highest thread priority.
44 * @return - Highest thread priority.
50 * @brief This function returns the lowest thread priority.
56 * @return - Lowest thread priority.
62 * @brief This function returns the default thread priority.
68 * @return - Default thread priority.
88 * priority - Thread priority. Highest and lowest priorities can be received
103 int priority, void *args,
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| /trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Include/m-profile/ |
| D | cmsis_armclang_m.h | 947 \brief Get Priority Mask
948 \details Returns the current state of the priority mask bit from the Priority Mask Register.
949 \return Priority Mask value
962 \brief Get Priority Mask (non-secure)
963 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
964 \return Priority Mask value
977 \brief Set Priority Mask
978 \details Assigns the given value to the Priority Mask Register.
979 \param [in] priMask Priority Mask
989 \brief Set Priority Mask (non-secure)
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| D | cmsis_clang_m.h | 948 \brief Get Priority Mask
949 \details Returns the current state of the priority mask bit from the Priority Mask Register.
950 \return Priority Mask value
963 \brief Get Priority Mask (non-secure)
964 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
965 \return Priority Mask value
978 \brief Set Priority Mask
979 \details Assigns the given value to the Priority Mask Register.
980 \param [in] priMask Priority Mask
990 \brief Set Priority Mask (non-secure)
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| D | cmsis_tiarmclang_m.h | 947 \brief Get Priority Mask
948 \details Returns the current state of the priority mask bit from the Priority Mask Register.
949 \return Priority Mask value
962 \brief Get Priority Mask (non-secure)
963 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
964 \return Priority Mask value
977 \brief Set Priority Mask
978 \details Assigns the given value to the Priority Mask Register.
979 \param [in] priMask Priority Mask
989 \brief Set Priority Mask (non-secure)
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| D | cmsis_gcc_m.h | 1131 \brief Get Priority Mask
1132 \details Returns the current state of the priority mask bit from the Priority Mask Register.
1133 \return Priority Mask value
1146 \brief Get Priority Mask (non-secure)
1147 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
1148 \return Priority Mask value
1161 \brief Set Priority Mask
1162 \details Assigns the given value to the Priority Mask Register.
1163 \param [in] priMask Priority Mask
1173 \brief Set Priority Mask (non-secure)
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| /trusted-firmware-m-latest/secure_fw/spm/include/ |
| D | tfm_arch.h | 55 /* The lowest secure interrupt priority */
59 * Although the priority of the secure PendSV must be the lowest possible
64 * FAULTMASK_NS, PRIMASK_NS or BASEPRI_NS register to boost its priority
66 * For this reason, set the priority of the PendSV interrupt to the next
67 * priority level configurable on the platform, just below 0x80.
78 * FAULTMASK_NS, PRIMASK_NS or BASEPRI_NS register to boost its priority
80 * execution, set the priority of Secure thread mode execution to this value.
85 /* If TZ is not in use, we have the full priority range available */
253 /* Set secure exceptions priority. */
257 /* Check secure exception priority */
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| /trusted-firmware-m-latest/platform/ext/target/stm/b_u585i_iot02a/include/ |
| D | b_u585i_iot02a_conf.h | 57 #define BSP_BUTTON_USER_IT_PRIORITY 15U /* Default is lowest priority level */
59 /* Audio interrupt priority */
60 #define BSP_AUDIO_IN_IT_PRIORITY 15U /* Default is lowest priority level */
62 /* CAMERA interrupt priority */
63 #define BSP_CAMERA_IT_PRIORITY 14U /* Default is lowest priority level */
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| /trusted-firmware-m-latest/docs/design_docs/software/ |
| D | tfm_cooperative_scheduling_rules.rst | 83 1. **All of the SPE interrupts must have higher priority than NSPE interrupts**
91 the SPM may choose to switch the current running SPE context based on priority.
116 4. **All of the interrupts belonging to a partition must have same priority.**
196 1. **A higher priority NSPE interrupt is allowed to preempt a lower priority**
199 2. **A higher priority SPE interrupt is allowed to preempt a lower priority**
206 5. **All interrupts belonging to a service must have same priority**
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| /trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/hal/Inc/ |
| D | stm32u5xx_hal_cortex.h | 96 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
99 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority,
101 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority,
103 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority,
105 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority,
107 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority,
311 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) argument
313 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) argument
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| /trusted-firmware-m-latest/secure_fw/include/ |
| D | build_config_check.h | 37 /* Check if there are unsupported thread priority. */
46 #error "Partition priority converting to thread priority error!"
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