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/trusted-firmware-m-3.4.0/secure_fw/spm/cmsis_psa/
Dthread.h21 /* Priorities. Lower value has higher priority */
40 uint8_t priority; /* Priority */ member
60 * priority - Initial priority
63 (p_thrd)->priority = (uint8_t)(prio); \
70 * Set thread priority.
74 * priority - Priority value (0~255)
77 * The new priority may not take effect immediately.
79 #define THRD_SET_PRIORITY(p_thrd, priority) \ argument
80 p_thrd->priority = (uint8_t)(priority)
Dthread.c28 * First runnable thread has highest priority since threads are in thrd_next()
29 * sorted by priority. in thrd_next()
40 if (*head == NULL || (node->priority <= (*head)->priority)) { in insert_by_prior()
46 while (iter->next && (node->priority > iter->next->priority)) { in insert_by_prior()
59 /* Insert a new thread with priority */ in thrd_start()
80 ((RNBL_HEAD == NULL) || (p_thrd->priority < RNBL_HEAD->priority))) { in thrd_set_state()
/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32l5xx/hal/Src/
Dstm32l5xx_hal_cortex.c23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
24 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
28 The pending IRQ priority will be managed only by the sub priority.
30 -@- IRQ priority order (sorted by highest to lowest priority):
31 (+@) Lowest pre-emption priority
32 (+@) Lowest sub priority
33 (+@) Lowest hardware priority (IRQ number)
44 (++) Configures the SysTick IRQ priority to the lowest value (0x07).
55 (+) You can change the SysTick IRQ priority by calling the
68 The table below gives the allowed values of the pre-emption priority and subpriority according
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/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32u5xx/hal/Src/
Dstm32u5xx_hal_cortex.c35 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
36 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
40 The pending IRQ priority will be managed only by the sub priority.
42 -@- IRQ priority order (sorted by highest to lowest priority):
43 (+@) Lowest pre-emption priority
44 (+@) Lowest sub priority
45 (+@) Lowest hardware priority (IRQ number)
56 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
67 (+) You can change the SysTick IRQ priority by calling the
95 The table below gives the allowed values of the pre-emption priority and subpriority according
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/trusted-firmware-m-3.4.0/platform/ext/target/stm/stm32l562e_dk/include/
Dstm32l562e_discovery_conf.h37 /* Button interrupt priority */
38 #define BSP_BUTTON_USER_IT_PRIORITY 0x07UL /* Default is lowest priority level */
40 /* IDD interrupt priority */
41 #define BSP_IDD_IT_PRIORITY 0x07UL /* Default is lowest priority level */
43 /* TS interrupt priority */
44 #define BSP_TS_IT_PRIORITY 0x07UL /* Default is lowest priority level */
47 #define BSP_AUDIO_OUT_IT_PRIORITY 0x07UL /* Default is lowest priority level */
48 #define BSP_AUDIO_IN_IT_PRIORITY 0x07UL /* Default is lowest priority level */
50 /* SD card interrupt priority */
51 #define BSP_SD_IT_PRIORITY 0x07UL /* Default is lowest priority level */
/trusted-firmware-m-3.4.0/platform/ext/cmsis/
Dcore_cm0plus.h339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
368 …__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Register…
842 \brief Set Interrupt Priority
843 \details Sets the priority of a device specific interrupt or a processor exception.
847 \param [in] priority Priority to set.
848 \note The priority cannot be set for every processor exception.
850 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) in __NVIC_SetPriority() argument
855 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
860 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
866 \brief Get Interrupt Priority
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Dcmsis_armclang.h991 \brief Get Priority Mask
992 \details Returns the current state of the priority mask bit from the Priority Mask Register.
993 \return Priority Mask value
1006 \brief Get Priority Mask (non-secure)
1007 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
1008 \return Priority Mask value
1021 \brief Set Priority Mask
1022 \details Assigns the given value to the Priority Mask Register.
1023 \param [in] priMask Priority Mask
1033 \brief Set Priority Mask (non-secure)
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Dcore_cm4.h423 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
453 …__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Register…
1645 \brief Set Priority Grouping
1646 \details Sets the priority grouping field using the required unlock sequence.
1649 In case of a conflict between priority grouping and available
1650 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1651 \param [in] PriorityGroup Priority grouping field.
1662 …orityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ in __NVIC_SetPriorityGrouping()
1668 \brief Get Priority Grouping
1669 \details Reads the priority grouping field from the NVIC Interrupt Controller.
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Dcmsis_armclang_ltm.h980 \brief Get Priority Mask
981 \details Returns the current state of the priority mask bit from the Priority Mask Register.
982 \return Priority Mask value
995 \brief Get Priority Mask (non-secure)
996 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
997 \return Priority Mask value
1010 \brief Set Priority Mask
1011 \details Assigns the given value to the Priority Mask Register.
1012 \param [in] priMask Priority Mask
1022 \brief Set Priority Mask (non-secure)
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Dcore_cm23.h367 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
396 …__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Register…
1713 \brief Set Interrupt Priority
1714 \details Sets the priority of a device specific interrupt or a processor exception.
1718 \param [in] priority Priority to set.
1719 \note The priority cannot be set for every processor exception.
1721 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) in __NVIC_SetPriority() argument
1726 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
1731 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in __NVIC_SetPriority()
1737 \brief Get Interrupt Priority
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Dcore_cm33.h482 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
512 …__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Register…
2351 \brief Set Priority Grouping
2352 \details Sets the priority grouping field using the required unlock sequence.
2355 In case of a conflict between priority grouping and available
2356 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2357 \param [in] PriorityGroup Priority grouping field.
2368 …orityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ in __NVIC_SetPriorityGrouping()
2374 \brief Get Priority Grouping
2375 \details Reads the priority grouping field from the NVIC Interrupt Controller.
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Dcmsis_gcc.h1200 \brief Get Priority Mask
1201 \details Returns the current state of the priority mask bit from the Priority Mask Register.
1202 \return Priority Mask value
1215 \brief Get Priority Mask (non-secure)
1216 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
1217 \return Priority Mask value
1230 \brief Set Priority Mask
1231 \details Assigns the given value to the Priority Mask Register.
1232 \param [in] priMask Priority Mask
1242 \brief Set Priority Mask (non-secure)
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/trusted-firmware-m-3.4.0/lib/ext/cryptocell-312-runtime/host/src/tests/TestAL/pal/include/
Dtest_pal_thread.h38 * @brief This function returns the highest thread priority.
44 * @return - Highest thread priority.
50 * @brief This function returns the lowest thread priority.
56 * @return - Lowest thread priority.
62 * @brief This function returns the default thread priority.
68 * @return - Default thread priority.
88 * priority - Thread priority. Highest and lowest priorities can be received
103 int priority, void *args,
/trusted-firmware-m-3.4.0/platform/ext/target/stm/b_u585i_iot02a/include/
Db_u585i_iot02a_conf.h57 #define BSP_BUTTON_USER_IT_PRIORITY 15U /* Default is lowest priority level */
59 /* Audio interrupt priority */
60 #define BSP_AUDIO_IN_IT_PRIORITY 15U /* Default is lowest priority level */
62 /* CAMERA interrupt priority */
63 #define BSP_CAMERA_IT_PRIORITY 14U /* Default is lowest priority level */
/trusted-firmware-m-3.4.0/secure_fw/spm/include/
Dtfm_arch.h53 /* The lowest secure interrupt priority */
57 * Although the priority of the secure PendSV must be the lowest possible
62 * FAULTMASK_NS, PRIMASK_NS or BASEPRI_NS register to boost its priority
64 * For this reason, set the priority of the PendSV interrupt to the next
65 * priority level configurable on the platform, just below 0x80.
69 /* If TZ is not in use, we have the full priority range available */
266 /* Set secure exceptions priority. */
270 /* Check secure exception priority */
/trusted-firmware-m-3.4.0/docs/technical_references/design_docs/
Dtfm_cooperative_scheduling_rules.rst83 1. **All of the SPE interrupts must have higher priority than NSPE interrupts**
91 the SPM may choose to switch the current running SPE context based on priority.
116 4. **All of the interrupts belonging to a partition must have same priority.**
196 1. **A higher priority NSPE interrupt is allowed to preempt a lower priority**
199 2. **A higher priority SPE interrupt is allowed to preempt a lower priority**
206 5. **All interrupts belonging to a service must have same priority**
Dsecure_partition_manager.rst279 thread has the highest priority.
432 - Set SPM API thread priority as the highest.
514 - The background state has a higher execution priority than other states -
545 - The exception handler priority needs to be decided.
546 - Boost the secure handler mode priority to prevent NSPE from preempting SPE
549 secure fault with the highest priority can be a valid option.
607 The scheduling logic is put inside the PendSV mode. PendSV mode's priority
608 is set as one level higher than the default thread mode priority. If
609 `Trustzone-M` is present, the priority is set as the lowest just above NS
610 exception priority to prevent a preemption in secure exceptions.
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/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32u5xx/hal/Inc/
Dstm32u5xx_hal_cortex.h96 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
99 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority,
101 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority,
103 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority,
105 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority,
107 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority,
311 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) argument
313 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) argument
Dstm32u5xx_hal_dma.h74 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. member
101 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. member
458 /** @defgroup DMA_Priority_Level DMA Priority Level
459 * @brief DMA Priority Level
462 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight …
463 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight …
464 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight…
465 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority …
816 #define IS_DMA_PRIORITY(PRIORITY) \ argument
817 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \
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/trusted-firmware-m-3.4.0/secure_fw/include/
Dbuild_config_check.h37 /* Check if there are unsupported thread priority. */
46 #error "Partition priority converting to thread priority error!"
/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32l5xx/hal/Inc/
Dstm32l5xx_hal_cortex.h97 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
100 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
102 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
104 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
106 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
310 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) argument
312 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) argument
/trusted-firmware-m-3.4.0/tools/templates/
Dpartition_load_info.template99 #pragma location = ".part_load_priority_{{manifest.priority|lower}}"
103 __attribute__((used, section(".part_load_priority_{{manifest.priority|lower}}"))) = {
121 | PARTITION_PRI_{{manifest.priority}},
285 #pragma location=".bss.part_runtime_priority_{{manifest.priority|lower}}"
289 __attribute__((used, section(".bss.part_runtime_priority_{{manifest.priority|lower}}")));
292 #pragma location = ".bss.serv_runtime_priority_{{manifest.priority|lower}}"
296 __attribute__((used, section(".bss.serv_runtime_priority_{{manifest.priority|lower}}")));
/trusted-firmware-m-3.4.0/platform/ext/target/nordic_nrf/common/nrf5340/
Dnrfx_config_nrf5340_application.h183 // <o> NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
257 // <o> NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
425 // <o> NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
452 // <o> NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
526 // <o> NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
608 // <o> NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
681 // <o> NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
773 // <o> NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
846 // <o> NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
990 // <o> NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
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/trusted-firmware-m-3.4.0/platform/ext/target/cypress/psoc64/
Dtfm_peripherals_def.h19 * Quantized default IRQ priority, the value is:
20 * (Number of configurable priority) / 4: (1UL << __NVIC_PRIO_BITS) / 4
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an524/
Dtfm_peripherals_def.h19 * Quantized default IRQ priority, the value is:
20 * (Number of configurable priority) / 4: (1UL << __NVIC_PRIO_BITS) / 4

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