Home
last modified time | relevance | path

Searched +full:prescale +full:- +full:scl +full:- +full:low (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/dts/bindings/i2c/
Dite,enhance-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,enhance-i2c"
8 include: ite,common-i2c.yaml
11 prescale-scl-low:
15 the SCL low period. When set to >= 1, it will increase the
16 low period of the SCL clock and so reduce the signal frequency.
17 The resulting SCL cycle time is given by the following formula:
18 SCL cycle = 2 * (psr + prescale_tweak + 2) *
21 data-hold-time:
25 - 3
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_ite_enhance.c4 * SPDX-License-Identifier: Apache-2.0
23 #include "i2c-priv.h"
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
67 /* SCL GPIO cells */
83 SCL = 0, enumerator
231 struct i2c_enhance_data *data = dev->data; in i2c_parsing_return_value()
233 if (!data->err) { in i2c_parsing_return_value()
238 if (data->err == ETIMEDOUT) { in i2c_parsing_return_value()
239 return -ETIMEDOUT; in i2c_parsing_return_value()
243 if (data->err == E_HOSTA_ACK) { in i2c_parsing_return_value()
[all …]