Home
last modified time | relevance | path

Searched full:pmc (Results 1 – 25 of 60) sorted by relevance

123

/Zephyr-Core-3.6.0/soc/arm/atmel_sam/common/
Dsoc_pmc.h9 * @brief Atmel SAM MCU family Power Management Controller (PMC) module
116 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | reg_val; in soc_pmc_mck_set_prescaler()
118 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { in soc_pmc_mck_set_prescaler()
152 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | reg_val; in soc_pmc_mck_set_divider()
154 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { in soc_pmc_mck_set_divider()
167 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | (uint32_t)source; in soc_pmc_mck_set_source()
169 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { in soc_pmc_mck_set_source()
181 PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN; in soc_pmc_switch_mainck_to_fastrc()
184 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { in soc_pmc_switch_mainck_to_fastrc()
188 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) in soc_pmc_switch_mainck_to_fastrc()
[all …]
Dsoc_pmc.c7 * @brief Atmel SAM MCU family Power Management Controller (PMC) module
24 PMC->PMC_PCER0 = BIT(id); in soc_pmc_peripheral_enable()
27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
41 PMC->PMC_PCDR0 = BIT(id); in soc_pmc_peripheral_disable()
44 PMC->PMC_PCDR1 = BIT(id & 0x1F); in soc_pmc_peripheral_disable()
58 return (PMC->PMC_PCSR0 & BIT(id)) != 0; in soc_pmc_peripheral_is_enabled()
61 return (PMC->PMC_PCSR1 & BIT(id & 0x1F)) != 0; in soc_pmc_peripheral_is_enabled()
/Zephyr-Core-3.6.0/dts/arm/atmel/
Dsame70.dtsi51 pmc: pmc@400e0600 { label
52 compatible = "atmel,sam-pmc";
70 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
87 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
98 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
109 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
120 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
130 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
148 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
[all …]
Dsam3x.dtsi32 pmc: pmc@400e0600 { label
33 compatible = "atmel,sam-pmc";
57 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
81 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
90 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
101 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
111 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
119 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
127 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
135 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
[all …]
Dsam4e.dtsi41 pmc: pmc@400e0400 { label
42 compatible = "atmel,sam-pmc";
64 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
73 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
82 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
100 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
109 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
120 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
[all …]
Dsam4s.dtsi43 pmc: pmc@400e0400 { label
44 compatible = "atmel,sam-pmc";
66 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
83 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
92 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
103 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
115 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
123 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
131 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
139 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
[all …]
Dsam4l.dtsi53 pmc: pmc@400e0000 { label
54 compatible = "atmel,sam-pmc";
86 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
96 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
106 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
116 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
126 clocks = <&pmc PMC_TYPE_PERIPHERAL 1>;
136 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
143 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
150 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
[all …]
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/
Dpmc_interface.h18 * The requesting agent will write the PMC command op-code into this field.
23 * When the PMC has completed the API command, the PMC will write a completion code (CC) back into
50 * responding agent. When this bit is set it will prompt the PMC to execute the command placed in
51 * the mailbox. The PMC will clear this flag after the command has been processed and a completion
58 /* PMC operation codes */
61 * No operation - PMC FW will clear the run / busy bit and return a success response
67 * param_1 - Pass back the PMC ACE protocol version - the initial version is 0.
Dcomm_widget_messages.c15 * Report number of used HP-SRAM memory banks to the PMC, unit is 32 KB.
/Zephyr-Core-3.6.0/dts/bindings/clock/
Datmel,sam-pmc.yaml5 Atmel Power Management Controller (PMC)
7 The Power Management Controller (PMC) optimizes power consumption by
8 controlling all system and user peripheral clocks. The PMC enables/disables
16 clocks = <&pmc PMC_TYPE_PERIPHERAL p-id>;
34 compatible: "atmel,sam-pmc"
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_control_sam_pmc.c29 LOG_ERR("The PMC config can not be NULL."); in atmel_sam_clock_control_on()
40 LOG_ERR("The PMC clock type is not implemented."); in atmel_sam_clock_control_on()
55 LOG_ERR("The PMC config can not be NULL."); in atmel_sam_clock_control_off()
66 LOG_ERR("The PMC clock type is not implemented."); in atmel_sam_clock_control_off()
82 LOG_ERR("The PMC config can not be NULL."); in atmel_sam_clock_control_get_rate()
93 LOG_ERR("The PMC clock type is not implemented."); in atmel_sam_clock_control_get_rate()
112 LOG_ERR("The PMC config can not be NULL."); in atmel_sam_clock_control_get_status()
125 LOG_ERR("The PMC clock type is not implemented."); in atmel_sam_clock_control_get_status()
/Zephyr-Core-3.6.0/soc/arm/atmel_sam/same70/
Dsoc_config.c40 PMC->PMC_SCDR = PMC_SCDR_PCK3; in atmel_same70_config()
41 while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { in atmel_same70_config()
45 PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; in atmel_same70_config()
47 PMC->PMC_SCER = PMC_SCER_PCK3; in atmel_same70_config()
49 while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { in atmel_same70_config()
/Zephyr-Core-3.6.0/soc/arm/atmel_sam/samv71/
Dsoc_config.c44 PMC->PMC_SCDR = PMC_SCDR_PCK3; in atmel_samv71_config()
45 while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { in atmel_samv71_config()
49 PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; in atmel_samv71_config()
51 PMC->PMC_SCER = PMC_SCER_PCK3; in atmel_samv71_config()
53 while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { in atmel_samv71_config()
/Zephyr-Core-3.6.0/drivers/pinctrl/
Dpinctrl_rzt2m.c17 #define PMC(port) (PORT_NSR + 0x400 + port) macro
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin() local
50 /* Set proper bit in the PMC register to use the pin as a peripheral IO. */ in pinctrl_configure_pin()
51 sys_write8(pmc | BIT(pin->pin), PMC(pin->port)); in pinctrl_configure_pin()
/Zephyr-Core-3.6.0/soc/arm/nxp_s32/s32k3/
DKconfig.soc49 When enabling PLL as system clock, the PMC last mile regulator should
58 VRC_CTRL pin and is controlled by the PMC to regulate a voltage of
/Zephyr-Core-3.6.0/drivers/misc/timeaware_gpio/
DKconfig.timeaware_gpio_intel1 # INTEL PMC TGPIO configuration options
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/
Dadsp_comm_widget.h6 /* Report number of used HP-SRAM memory banks to the PMC, unit is 32 KB. */
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
Datmel_sam_pmc.h13 #define SAM_DT_PMC_CONTROLLER DEVICE_DT_GET(DT_NODELABEL(pmc))
/Zephyr-Core-3.6.0/drivers/usb/device/
Dusb_dc_sam_usbhs.c75 PMC->CKGR_UCKR |= CKGR_UCKR_UPLLEN; in usb_dc_enable_clock()
78 while (!(PMC->PMC_SR & PMC_SR_LOCKU)) { in usb_dc_enable_clock()
86 PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2; in usb_dc_enable_clock()
87 PMC->PMC_USB = PMC_USB_USBDIV(9) | PMC_USB_USBS; in usb_dc_enable_clock()
90 PMC->PMC_SCER |= PMC_SCER_USBCLK; in usb_dc_enable_clock()
98 PMC->PMC_SCER &= ~PMC_SCER_USBCLK; in usb_dc_disable_clock()
101 PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; in usb_dc_disable_clock()
317 /* Enable USBHS clock in PMC */ in usb_dc_attach()
377 /* Disable USBHS clock in PMC */ in usb_dc_detach()
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k6x/
Dsoc.c137 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; in k6x_init()
141 PMC->REGSC |= PMC_REGSC_BGBE_MASK; in k6x_init()
/Zephyr-Core-3.6.0/drivers/hwinfo/
Dhwinfo_sam_rstc.c63 /* Enable RSTC in PMC */ in hwinfo_rstc_init()
/Zephyr-Core-3.6.0/drivers/can/
Dcan_sam.c84 PMC->PMC_SCER |= PMC_SCER_PCK5; in can_sam_clock_enable()
86 /* Enable CAN clock in PMC */ in can_sam_clock_enable()
/Zephyr-Core-3.6.0/soc/arm/nxp_s32/common/
Dpower_soc.c75 /* PMC Configuration Register (CONFIG) */ in nxp_s32_power_init()
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/kv5x/
Dsoc.c84 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; in kv5x_init()
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k8x/
Dsoc.c102 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; in k8x_init()

123