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/Zephyr-latest/dts/bindings/dma/
Darm,dma-pl330.yaml5 PL330 DMA Controller
10 Example for pl330 DMA Controller
11 pl330: pl330@48300000 {
12 compatible = "arm,dma-pl330";
22 dmas = <&pl330 0>, <&pl330 1>;
25 compatible: "arm,dma-pl330"
/Zephyr-latest/dts/common/broadcom/
Dviper-common.dtsi30 pl330: pl330@48300000 { label
31 compatible = "arm,dma-pl330";
53 dmas = <&pl330 0>, <&pl330 1>;
/Zephyr-latest/drivers/dma/
DKconfig.dma_pl3306 prompt "PL330 DMA driver"
10 This option enables support of pl330 DMA Controller.
Ddma_pl330.h17 * Burst length is encoded in following format for pl330
25 * Burst size is encoded in following format for pl330
39 * PL330 works only on 4GB boundary.
40 * PL330 has 32bit registers for source and destination addresses
44 /* PL330 supports max 16MB dma based on AXI bus size */
47 /* Maximum possible values for PL330 ucode loop counters */
Ddma_pl330.c341 * Pl330 supports only 4GB boundary, but boundary region can be in dma_pl330_xfer()
344 * in pl330 registers and higher 4bit address are configured in in dma_pl330_xfer()
354 LOG_ERR("Failed to setup channel for DMA PL330"); in dma_pl330_xfer()
361 LOG_ERR("Failed to start DMA PL330"); in dma_pl330_xfer()
367 LOG_ERR("Failed waiting to finish DMA PL330"); in dma_pl330_xfer()
387 * Pl330 has only 32bit registers and supports 4GB memory. in dma_pl330_handle_boundary()
434 * Pl330 has only 32bit registers and supports 4GB memory. in dma_pl330_submit()
/Zephyr-latest/dts/arm/intel_socfpga_std/
Dsocfpga.dtsi58 compatible = "arm,pl330-cache";