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/hal_atmel-3.7.0/asf/sam0/include/samd20/instance/
Dport.h91 #define PORT_BITS 64 // Number of PORT pins
92 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for DIR of all pins
93 …e PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
95 …fine PORT_DRVSTR_DEFAULT_VAL { 0xDBFFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
96 …ORT_DRVSTR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
98 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for INEN of all pins
99 … PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
101 …fine PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
102 …ORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
103 #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for OUT of all pins
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/hal_atmel-3.7.0/asf/sam0/include/samd21/instance/
Dport.h90 #define PORT_BITS 84 // Number of PORT pins
91 …_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
92 …MPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
94 …VSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
95 …MPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
97 …INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
98 …MPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
100 …RAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
101 …MPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
102 …_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
[all …]
/hal_atmel-3.7.0/asf/sam0/include/samr21/instance/
Dport.h116 #define PORT_BITS 84 // Number of PORT pins
117 …_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
118 …MPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
120 …VSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
121 …MPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
123 …INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
124 …MPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
126 …RAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
127 …MPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
128 …_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
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/hal_atmel-3.7.0/pinconfigs/
DREADME.md5 pin to a peripheral signal which multiplex, at end, I/O lines pins. For example,
32 of a different number of pins.
33 - `pins` (required): The pin map itself
38 aleatory pins to help understand the definition schema.
43 # - 48 pins: g
44 # - 64 pins: j
45 # - 100 pins: n
46 # - 120/128 pins: p (package exception)
73 pins:
130 Some sam0 SoC have optimized pins in some revisions. To differentiate those a
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Dsam-l21.yml9 # - 32 pins: e
10 # - 48 pins: g
11 # - 64 pins: j
35 pins:
Dsam-4s-4sa-4sd.yml9 # - 48 pins: a
10 # - 64 pins: b
11 # - 100 pins: c
31 pins:
Dsam-r21.yml9 # - 32 pins: e
10 # - 48 pins: g
26 pins:
Dsam-c2x.yml9 # - 32 pins: e
10 # - 48 pins: g
11 # - 64 pins: j
12 # - 100 pins: n
40 pins:
Dsam-d2x-da1-abcd.yml10 # - 32 pins: e
11 # - 48 pins: g
12 # - 64 pins: j
47 pins:
Dsam-3x.yml9 # - 100 pins: c
10 # - 144 pins: e
11 # - 217 pins: h
29 pins:
Dsam-d5x-e5x.yml9 # - 48 pins: g
10 # - 64 pins: j
11 # - 100 pins: n
12 # - 120/128 pins: p (package exception)
36 pins:
Dsam-4l.yml9 # - 48 pins: a
10 # - 64 pins: b
11 # - 100 pins: c
29 pins:
Dsam-s70-e70-v7x.yml9 # - 64 pins: j
10 # - 100 pins: n
11 # - 144 pins: q
30 pins:
Dsam-4e.yml9 # - 100 pins: c
10 # - 144 pins: e
26 pins:
Dsam-r34-r35.yml9 # - 64 pins: j
28 pins:
/hal_atmel-3.7.0/scripts/
Dsampinctrl.py148 pins: Pins description.
151 Dictionary with pins configuration.
167 pins: Pins description.
170 Dictionary with pins configuration.
186 def build_atmel_sam_pin_cfgs(serie, variant, pins): argument
192 pins: Pins description.
195 Dictionary with pins configuration.
200 pins = OrderedDict(natsorted(pins.items(), key=lambda kv: kv[0]))
202 for pin, pin_cfg in pins.items():
253 pins = config["pins"]
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/hal_atmel-3.7.0/scripts/tests/sampinctrl/data/
Dsam-pinctrl.yml21 pins:
/hal_atmel-3.7.0/asf/sam0/include/saml21/instance/
Dccl.h54 #define CCL_IO_NUM 12 // Numer of input pins
/hal_atmel-3.7.0/asf/sam0/include/samr34/instance/
Dccl.h54 #define CCL_IO_NUM 12 // Numer of input pins
/hal_atmel-3.7.0/asf/sam0/include/samr35/instance/
Dccl.h54 #define CCL_IO_NUM 12 // Numer of input pins
/hal_atmel-3.7.0/asf/sam0/include/samc20/instance/
Dccl.h54 #define CCL_IO_NUM 12 // Numer of input pins
/hal_atmel-3.7.0/asf/sam0/include/samc21/instance/
Dccl.h54 #define CCL_IO_NUM 12 // Numer of input pins
/hal_atmel-3.7.0/asf/common/components/wifi/winc1500/bsp/include/
Dnm_bsp.h146 …ong>S</strong>upport <strong>P</strong>ackage) such as Reset and Chip Enable Pins for WINC, delays,
/hal_atmel-3.7.0/asf/sam/include/sam4l/component/
Dcatb.h476 uint32_t NPINS:8; /*!< bit: 0.. 7 Number of Pins */
487 #define CATB_PARAMETER_NPINS_Pos 0 /**< \brief (CATB_PARAMETER) Number of Pins */
/hal_atmel-3.7.0/asf/sam/include/samv71b/component/
Di2sc.h129 …chronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock o…
131 …chronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock o…

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