| /Zephyr-Core-3.6.0/dts/bindings/gpio/ |
| D | renesas,ra-gpio.yaml | 14 port-irq0-pins:
16 description: Pins allow to assign port-irq0
18 port-irq1-pins:
20 description: Pins allow to assign port-irq1
22 port-irq2-pins:
24 description: Pins allow to assign port-irq2
26 port-irq3-pins:
28 description: Pins allow to assign port-irq3
30 port-irq4-pins:
32 description: Pins allow to assign port-irq4
[all …]
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| D | xlnx,ps-gpio.yaml | 10 ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,
11 which can be mapped in the system design tools (MIO pins), or SoC-
13 logic part of the SoC (EMIO pins).
16 of available GPIO pins differs between the two SoC families:
19 * Bank 0: MIO pins [31:00]
20 * Bank 1: MIO pins [53:32] (total: 54 MIO pins)
21 * Bank 2: EMIO pins [31:00]
22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
25 * Bank 0: MIO pins [25:00]
26 * Bank 1: MIO pins [51:26]
[all …]
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| D | particle-gen3-header.yaml | 5 GPIO pins exposed on Particle Gen3 (Feather) headers.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
16 This binding provides a nexus mapping for 22 pins where parent pins
17 0 through 8 correspond to the pins on the 12-pin header, starting
18 from the bottom; and pins 9 through 21 correspond to pins on the
|
| D | adafruit-feather-header.yaml | 5 GPIO pins exposed on Adafruit Feather headers.
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
15 This binding provides a nexus mapping for 21 pins where parent pins 0
16 through 5 correspond to A0 through A5, and parent pins 6 through 20
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| D | arduino-mkr-header.yaml | 5 GPIO pins exposing on Arduino MKR headers.
15 and SPI peripheral pins are also there. The end 2 pins are simple GPIO pins.
17 This binding provides a nexus mapping for 22 pins where parent pins 0
18 through 14 correspond to D0 through D21, and parent pins 15 through 21
|
| D | arduino-nano-header-r3.yaml | 5 GPIO pins exposed on Arduino Nano (R3) headers.
10 and GND (pin 4) pins are not exposed by this binding.
13 power supply and reset pins are not exposed by this binding.
15 This binding provides a nexus mapping for 22 pins where parent pins 0
16 through 13 correspond to D0 through D13, and parent pins 14 through 21
|
| D | digilent,pmod.yaml | 5 GPIO pins exposed on a Digilent Pmod interface.
7 This binding provides a nexus mapping for 8 pins where parent pins 0
8 through 3 correspond to IO1 through IO4, and parent pins 4 through 7
21 is a proper subset of the 12-pin connector. In that case parent pins 4
|
| D | arduino-header-r3.yaml | 6 GPIO pins exposed on Arduino Uno (R3) headers.
12 * An 8-pin Power Supply header. No pins on this header are exposed
20 towards the top, skipping two pins, then finishing with D14 and
23 This binding provides a nexus mapping for 20 pins where parent pins 0
24 through 5 correspond to A0 through A5, and parent pins 6 through 21
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| /Zephyr-Core-3.6.0/tests/drivers/pinctrl/nrf/src/ |
| D | main.c | 27 zassert_equal(NRF_GET_FUN(scfg->pins[0]), NRF_FUN_UART_TX); in ZTEST()
28 zassert_equal(NRF_GET_LP(scfg->pins[0]), NRF_LP_DISABLE); in ZTEST()
29 zassert_equal(NRF_GET_DRIVE(scfg->pins[0]), NRF_DRIVE_S0S1); in ZTEST()
30 zassert_equal(NRF_GET_PULL(scfg->pins[0]), NRF_PULL_NONE); in ZTEST()
31 zassert_equal(NRF_GET_PIN(scfg->pins[0]), 1U); in ZTEST()
33 zassert_equal(NRF_GET_FUN(scfg->pins[1]), NRF_FUN_UART_RTS); in ZTEST()
34 zassert_equal(NRF_GET_LP(scfg->pins[1]), NRF_LP_DISABLE); in ZTEST()
35 zassert_equal(NRF_GET_DRIVE(scfg->pins[1]), NRF_DRIVE_S0S1); in ZTEST()
36 zassert_equal(NRF_GET_PULL(scfg->pins[1]), NRF_PULL_NONE); in ZTEST()
37 zassert_equal(NRF_GET_PIN(scfg->pins[1]), 2U); in ZTEST()
[all …]
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| /Zephyr-Core-3.6.0/drivers/pinctrl/ |
| D | pinctrl_imx.c | 11 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, in pinctrl_configure_pins() argument
14 /* configure all pins */ in pinctrl_configure_pins()
16 uint32_t mux_register = pins[i].pinmux.mux_register; in pinctrl_configure_pins()
17 uint32_t mux_mode = pins[i].pinmux.mux_mode; in pinctrl_configure_pins()
18 uint32_t input_register = pins[i].pinmux.input_register; in pinctrl_configure_pins()
19 uint32_t input_daisy = pins[i].pinmux.input_daisy; in pinctrl_configure_pins()
20 uint32_t config_register = pins[i].pinmux.config_register; in pinctrl_configure_pins()
21 uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; in pinctrl_configure_pins()
24 (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register); in pinctrl_configure_pins()
27 if (pins[i].pinmux.gpr_val) { in pinctrl_configure_pins()
[all …]
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| D | pinctrl_ite_it8xxx2.c | 51 * (this bit apply to all pins)
56 * (this bit apply to all pins)
69 static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins) in pinctrl_it8xxx2_set() argument
71 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
73 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
74 uint8_t pin = pins->pin; in pinctrl_it8xxx2_set()
131 static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins) in pinctrl_gpio_it8xxx2_configure_pins() argument
133 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_gpio_it8xxx2_configure_pins()
135 uint8_t pin = pins->pin; in pinctrl_gpio_it8xxx2_configure_pins()
142 if (pinctrl_it8xxx2_set(pins)) { in pinctrl_gpio_it8xxx2_configure_pins()
[all …]
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| D | pinctrl_xlnx_zynq.c | 29 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) in pinctrl_configure_pins() argument
47 __ASSERT_NO_MSG(pins[i].offset <= MIO_PIN_53_OFFSET || in pinctrl_configure_pins()
48 pins[i].offset == SD0_WP_CD_SEL_OFFSET || in pinctrl_configure_pins()
49 pins[i].offset == SD1_WP_CD_SEL_OFFSET); in pinctrl_configure_pins()
51 addr = base + pins[i].offset; in pinctrl_configure_pins()
59 LOG_DBG("0x%04x: mask 0x%08x, val 0x%08x", addr, pins[i].mask, pins[i].val); in pinctrl_configure_pins()
62 val &= ~(pins[i].mask); in pinctrl_configure_pins()
63 val |= pins[i].val; in pinctrl_configure_pins()
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| /Zephyr-Core-3.6.0/tests/drivers/pinctrl/api/src/ |
| D | main.c | 48 zassert_equal(TEST_GET_PIN(scfg->pins[0]), 0); in ZTEST()
49 zassert_equal(TEST_GET_PULL(scfg->pins[0]), TEST_PULL_UP); in ZTEST()
50 zassert_equal(TEST_GET_PIN(scfg->pins[1]), 1); in ZTEST()
51 zassert_equal(TEST_GET_PULL(scfg->pins[1]), TEST_PULL_DOWN); in ZTEST()
73 zassert_equal(TEST_GET_PIN(scfg->pins[0]), 10); in ZTEST()
74 zassert_equal(TEST_GET_PULL(scfg->pins[0]), TEST_PULL_DISABLE); in ZTEST()
75 zassert_equal(TEST_GET_PIN(scfg->pins[1]), 11); in ZTEST()
76 zassert_equal(TEST_GET_PULL(scfg->pins[1]), TEST_PULL_DISABLE); in ZTEST()
77 zassert_equal(TEST_GET_PIN(scfg->pins[2]), 12); in ZTEST()
78 zassert_equal(TEST_GET_PULL(scfg->pins[2]), TEST_PULL_DISABLE); in ZTEST()
[all …]
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| /Zephyr-Core-3.6.0/tests/drivers/pinctrl/api/ |
| D | app.overlay | 14 pins = <0>;
18 pins = <1>;
26 pins = <0>, <1>;
33 pins = <2>;
37 pins = <3>;
45 pins = <2>, <3>;
52 pins = <10>, <11>, <12>;
59 pins = <10>;
62 pins = <11>;
66 pins = <12>;
|
| /Zephyr-Core-3.6.0/drivers/gpio/ |
| D | gpio_sx1509b.c | 29 /* Number of pins supported by the device */
32 /* Max to select all pins supported on the device. */
38 /** Cache of the output configuration and data of the pins. */
146 /* Intensity register addresses for all 16 pins */
231 uint32_t pins) in sx1509_int_cb() argument
236 ARG_UNUSED(pins); in sx1509_int_cb()
244 struct sx1509b_pin_state *pins, bool data_first) in write_pin_state() argument
248 struct sx1509b_pin_state pins; in write_pin_state() member
253 pin_buf.pins.input_disable = sys_cpu_to_be16(pins->input_disable); in write_pin_state()
254 pin_buf.pins.long_slew = sys_cpu_to_be16(pins->long_slew); in write_pin_state()
[all …]
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| D | gpio_rpi_pico.c | 93 /* First handle push-pull pins: */ in gpio_rpi_port_set_masked_raw()
95 /* Then handle open-drain pins: */ in gpio_rpi_port_set_masked_raw()
97 /* Then handle open-source pins: */ in gpio_rpi_port_set_masked_raw()
103 uint32_t pins) in gpio_rpi_port_set_bits_raw() argument
106 /* First handle push-pull pins: */ in gpio_rpi_port_set_bits_raw()
107 gpio_set_mask(pins & ~data->single_ended_mask); in gpio_rpi_port_set_bits_raw()
108 /* Then handle open-drain pins: */ in gpio_rpi_port_set_bits_raw()
109 gpio_set_dir_in_masked(pins & data->single_ended_mask & data->open_drain_mask); in gpio_rpi_port_set_bits_raw()
110 /* Then handle open-source pins: */ in gpio_rpi_port_set_bits_raw()
111 gpio_set_dir_out_masked(pins & data->single_ended_mask & ~data->open_drain_mask); in gpio_rpi_port_set_bits_raw()
[all …]
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| D | gpio_cy8c95xx.c | 24 /** Cache of the output configuration and data of the pins. */
56 static int write_pin_state(const struct cy8c95xx_config *cfg, struct cy8c95xx_pin_state *pins) in write_pin_state() argument
61 pins->data_out); in write_pin_state()
71 rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_DIR, pins->dir); in write_pin_state()
76 rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_PULL_UP, pins->pull_up); in write_pin_state()
81 rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_PULL_DOWN, pins->pull_down); in write_pin_state()
92 struct cy8c95xx_pin_state *pins = &drv_data->pin_state; in cy8c95xx_config() local
106 WRITE_BIT(pins->pull_up, pin, (flags & GPIO_PULL_UP) != 0U); in cy8c95xx_config()
107 WRITE_BIT(pins->pull_down, pin, (flags & GPIO_PULL_DOWN) != 0U); in cy8c95xx_config()
118 pins->dir &= ~BIT(pin); in cy8c95xx_config()
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/test/ |
| D | vnd,pinctrl-test.yaml | 14 more groups, each defining the configuration for a set of pins.
19 pins sharing the same set of properties. Example:
25 /* configure pins 0 and 1 */
26 pins = <0>, <1>;
27 /* both pins 0 and 1 have pull-up enabled */
34 pins = <M>;
52 pins:
56 An array of pins sharing the same group properties. Each entry is a
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| /Zephyr-Core-3.6.0/dts/arm/renesas/ra/ |
| D | ra-cm4-common.dtsi | 133 port-irq2-pins = <2>;
134 port-irq3-pins = <4>;
135 port-irq6-pins = <0>;
136 port-irq7-pins = <1 15>;
137 port-irq10-pins = <5>;
138 port-irq15-pins = <11>;
154 port-irq0-pins = <5>;
155 port-irq1-pins = <1>;
156 port-irq2-pins = <0>;
157 port-irq3-pins = <10>;
[all …]
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| /Zephyr-Core-3.6.0/tests/drivers/sensor/adltc2990/boards/ |
| D | native_sim.overlay | 11 pins-v1-v2-current-resistor = <0>;
12 pins-v3-v4-current-resistor = <0>;
25 pins-v1-v2-current-resistor = <1000000>;
26 pins-v3-v4-current-resistor = <0>;
37 pins-v1-v2-current-resistor = <1000000>;
38 pins-v3-v4-current-resistor = <0>;
51 pins-v1-v2-current-resistor = <1000000>;
52 pins-v3-v4-current-resistor = <0>;
65 pins-v1-v2-current-resistor = <10000>;
66 pins-v3-v4-current-resistor = <100000>;
[all …]
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| /Zephyr-Core-3.6.0/samples/boards/nrf/dynamic_pinctrl/ |
| D | README.rst | 18 However, if a certain peripheral is routed to different sets of pins between
29 associated pins has not been initialized yet. Therefore, pay attention to the
35 The diagram below shows the pins assigned to the default and alternative
43 set of pins. The default set of pins is also exposed through the left USB
47 routed to the alternative set of pins.
69 1. Connect a USB-to-UART adapter to both sets of pins. If the board routes the
73 #. Open two serial terminals, one connected to the default set of pins and the
74 other connected to the alternative set of pins.
85 ``Hello World!`` printed on the default set of pins.
93 ``Hello World!`` printed on the alternative set of pins.
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| /Zephyr-Core-3.6.0/include/zephyr/drivers/gpio/ |
| D | gpio_emul.h | 32 * controllers as well as the number of pins for each controller
47 * @brief Modify the values of one or more emulated GPIO input @p pins
50 * @param pins The mask of pins that have changed
51 * @param values New values to assign to @p pins
56 int gpio_emul_input_set_masked(const struct device *port, gpio_port_pins_t pins,
76 * @brief Read the value of one or more emulated GPIO output @p pins
79 * @param pins The mask of pins that have changed
80 * @param values A pointer to where the value of @p pins will be stored
85 int gpio_emul_output_get_masked(const struct device *port, gpio_port_pins_t pins,
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| /Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 17 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
23 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
30 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
36 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
43 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
50 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
57 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
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| /Zephyr-Core-3.6.0/tests/drivers/pinctrl/gd32/src/ |
| D | main_afio.c | 26 pin = scfg->pins[0]; in ZTEST()
32 pin = scfg->pins[1]; in ZTEST()
39 pin = scfg->pins[2]; in ZTEST()
47 pin = scfg->pins[3]; in ZTEST()
58 pin = scfg->pins[4]; in ZTEST()
68 pin = scfg->pins[5]; in ZTEST()
76 pin = scfg->pins[6]; in ZTEST()
84 pin = scfg->pins[7]; in ZTEST()
92 pin = scfg->pins[8]; in ZTEST()
100 pin = scfg->pins[9]; in ZTEST()
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/pinctrl/ |
| D | nxp,lpc-iocon-pinctrl.yaml | 8 subgroup represents pins with shared configuration for that peripheral. The
9 'pinmux' property of each group selects the pins to be configured with these
10 properties. For example, here is a configuration for FLEXCOMM0 pins:
29 Values for I2C type and analog type pins have the following defaults:
96 analog type pins. Selects ASW0 on LPC55s3x family
101 when DIGIMODE=0. Only valid for analog type pins. Sets ASW1.
108 Pin output power source. Only valid for I2C mode pins running in I2C
120 I2C glitch filter speed. Only valid for I2C mode pins. Fast mode
128 I2C speed. Only valid for I2C mode pins. Fast mode should be used for
134 mode. Only valid for I2C mode pins in I2C mode
[all …]
|
