| /Zephyr-Core-2.7.6/drivers/modem/ |
| D | modem_pin.c | 25 return gpio_pin_get(ctx->pins[pin].gpio_port_dev, in modem_pin_read()
26 ctx->pins[pin].pin); in modem_pin_read()
35 return gpio_pin_set(ctx->pins[pin].gpio_port_dev, in modem_pin_write()
36 ctx->pins[pin].pin, value); in modem_pin_write()
45 return gpio_pin_configure(ctx->pins[pin].gpio_port_dev, in modem_pin_config()
46 ctx->pins[pin].pin, in modem_pin_config()
47 enable ? ctx->pins[pin].init_flags : in modem_pin_config()
57 ctx->pins[i].gpio_port_dev = in modem_pin_init()
58 device_get_binding(ctx->pins[i].dev_name); in modem_pin_init()
59 if (!ctx->pins[i].gpio_port_dev) { in modem_pin_init()
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| /Zephyr-Core-2.7.6/dts/bindings/flash_controller/ |
| D | nordic,nrf-qspi.yaml | 31 For pins P0.0 through P0.31, use the pin number. For example,
36 For pins P1.0 through P1.31, add 32 to the pin number. For
40 io-pins:
48 io-pins = <io0-pin io1-pin>; // two pins
50 io-pins = <io0-pin io1-pin io2-pin io3-pin>; // four pins
52 Either two or four pins must be configured using this property
55 csn-pins:
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| /Zephyr-Core-2.7.6/drivers/gpio/ |
| D | gpio_sx1509b.c | 28 /* Number of pins supported by the device */
31 /* Max to select all pins supported on the device. */
37 /** Cache of the output configuration and data of the pins. */
150 /* Intensity register addresses for all 16 pins */
240 uint32_t pins) in sx1509_int_cb() argument
245 ARG_UNUSED(pins); in sx1509_int_cb()
253 struct sx1509b_pin_state *pins, bool data_first) in write_pin_state() argument
257 struct sx1509b_pin_state pins; in write_pin_state() member
262 pin_buf.pins.input_disable = sys_cpu_to_be16(pins->input_disable); in write_pin_state()
263 pin_buf.pins.long_slew = sys_cpu_to_be16(pins->long_slew); in write_pin_state()
[all …]
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| D | gpio_cy8c95xx.c | 24 /** Cache of the output configuration and data of the pins. */
59 struct cy8c95xx_pin_state *pins) in write_pin_state() argument
64 CY8C95XX_REG_OUTPUT_DATA0 + cfg->port_num, pins->data_out); in write_pin_state()
76 CY8C95XX_REG_DIR, pins->dir); in write_pin_state()
82 CY8C95XX_REG_PULL_UP, pins->pull_up); in write_pin_state()
88 CY8C95XX_REG_PULL_DOWN, pins->pull_down); in write_pin_state()
99 struct cy8c95xx_pin_state *pins = &drv_data->pin_state; in cy8c95xx_config() local
118 WRITE_BIT(pins->pull_up, pin, (flags & GPIO_PULL_UP) != 0U); in cy8c95xx_config()
119 WRITE_BIT(pins->pull_down, pin, (flags & GPIO_PULL_DOWN) != 0U); in cy8c95xx_config()
130 pins->dir &= ~BIT(pin); in cy8c95xx_config()
[all …]
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| D | Kconfig.esp32 | 15 bool "ESP32 GPIO (pins 0-31)"
18 Include support for GPIO pins 0-31 on the ESP32.
21 bool "ESP32 GPIO (pins 32-39)"
24 Include support for GPIO pins 32-39 on the ESP32.
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| D | gpio_handlers.c | 43 gpio_port_pins_t pins) in z_vrfy_gpio_port_set_bits_raw() argument
47 pins); in z_vrfy_gpio_port_set_bits_raw()
52 gpio_port_pins_t pins) in z_vrfy_gpio_port_clear_bits_raw() argument
56 pins); in z_vrfy_gpio_port_clear_bits_raw()
61 gpio_port_pins_t pins) in z_vrfy_gpio_port_toggle_bits() argument
64 return z_impl_gpio_port_toggle_bits((const struct device *)port, pins); in z_vrfy_gpio_port_toggle_bits()
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| D | gpio_pca953x.c | 31 /* Number of pins supported by the device */
34 /* Max to select all pins supported on the device. */
37 /** Cache of the output configuration and data of the pins. */
74 * @brief Gets the state of input pins of the PCA953X I/O Port and
132 /* Find out which input pins have changed state */ in gpio_pca953x_handle_interrupt()
168 * @param pins Bitmask of pins that triggered interrupt
171 struct gpio_callback *gpio_cb, uint32_t pins) in gpio_pca953x_init_cb() argument
176 ARG_UNUSED(pins); in gpio_pca953x_init_cb()
186 struct pca953x_pin_state *pins = &drv_data->pin_state; in gpio_pca953x_config() local
229 pins->dir &= ~BIT(pin); in gpio_pca953x_config()
[all …]
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| D | gpio_creg_gpio.c | 97 gpio_port_pins_t pins) in port_set_bits() argument
99 return port_write(dev, pins, pins, 0); in port_set_bits()
103 gpio_port_pins_t pins) in port_clear_bits() argument
105 return port_write(dev, pins, 0, 0); in port_clear_bits()
109 gpio_port_pins_t pins) in port_toggle_bits() argument
111 return port_write(dev, 0, 0, pins); in port_toggle_bits()
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| D | gpio_emul.c | 49 * controller as well as all of the pins associated with it.
63 /** Number of pins available in the given GPIO controller instance */
100 * @brief Obtain a mask of pins that match all of the provided @p flags
102 * Use this function to see which pins match the current GPIO configuration.
110 * @return a mask of the pins with matching @p flags
133 * @brief Obtain a mask of pins that are configured as @ref GPIO_INPUT
139 * @return a mask of pins that are configured as @ref GPIO_INPUT
147 * @brief Obtain a mask of pins that are configured as @ref GPIO_OUTPUT
153 * @return a mask of pins that are configured as @ref GPIO_OUTPUT
260 * @param mask The mask of pins that have changed
[all …]
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| D | gpio_lpc11u6x.c | 126 * PIO0_4 and PIO0_5 are "true" open drain pins muxed with the I2C port in gpio_lpc11u6x_pin_configure()
138 * the other pins, function 0 must be selected. in gpio_lpc11u6x_pin_configure()
213 /* Update pins values. */ in gpio_lpc11u6x_port_set_masked_raw()
224 gpio_port_pins_t pins) in gpio_lpc11u6x_port_set_bits_raw() argument
230 gpio_regs->set[config->port_num] = pins; in gpio_lpc11u6x_port_set_bits_raw()
236 gpio_port_pins_t pins) in gpio_lpc11u6x_port_clear_bits_raw() argument
242 gpio_regs->clr[config->port_num] = pins; in gpio_lpc11u6x_port_clear_bits_raw()
248 gpio_port_pins_t pins) in gpio_lpc11u6x_port_toggle_bits() argument
254 gpio_regs->not[config->port_num] = pins; in gpio_lpc11u6x_port_toggle_bits()
430 uint32_t pins[3] = { 0, 0, 0 }; in gpio_lpc11u6x_isr() local
[all …]
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| /Zephyr-Core-2.7.6/dts/bindings/gpio/ |
| D | particle-gen3-header.yaml | 5 GPIO pins exposed on Particle Gen3 (Feather) headers.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
16 This binding provides a nexus mapping for 22 pins where parent pins
17 0 through 8 correspond to the pins on the 12-pin header, starting
18 from the bottom; and pins 9 through 21 correspond to pins on the
|
| D | adafruit-feather-header.yaml | 5 GPIO pins exposed on Adafruit Feather headers.
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
15 This binding provides a nexus mapping for 21 pins where parent pins 0
16 through 5 correspond to A0 through A5, and parent pins 6 through 20
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| D | arduino-header-r3.yaml | 6 GPIO pins exposed on Arduino Uno (R3) headers.
12 * An 8-pin Power Supply header. No pins on this header are exposed
20 towards the top, skipping two pins, then finishing with D14 and
23 This binding provides a nexus mapping for 20 pins where parent pins 0
24 through 5 correspond to A0 through A5, and parent pins 6 through 21
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| D | mikro-bus.yaml | 5 GPIO pins exposed on Mikro BUS headers.
14 This binding provides a nexus mapping for 10 pins, left side pins are
15 numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
16 (PWM - SDA). The bottom 2 pins on each side are used for input voltage
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| D | microbit,edge-connector.yaml | 5 GPIO pins exposed on BBC MicroBit headers.
10 There are 25 strips/pins including 5 rings for using with 4mm banana
18 with an 80w 1.27mm pitch that can be used to easily access these extra pins.
20 Only the pins on the front are connected to signals. The back rings are
|
| D | atmel-xplained-header.yaml | 5 GPIO pins exposed on Atmel Xplained headers.
8 one or more headers and can share pins. This connector was developed to
32 This binding provides a nexus mapping for 10 pins where pins are disposed
|
| /Zephyr-Core-2.7.6/include/drivers/gpio/ |
| D | gpio_emul.h | 32 * controllers as well as the number of pins for each controller
47 * @brief Modify the values of one or more emulated GPIO input @p pins
50 * @param pins The mask of pins that have changed
51 * @param values New values to assign to @p pins
56 int gpio_emul_input_set_masked(const struct device *port, gpio_port_pins_t pins,
76 * @brief Read the value of one or more emulated GPIO output @p pins
79 * @param pins The mask of pins that have changed
80 * @param values A pointer to where the value of @p pins will be stored
85 int gpio_emul_output_get_masked(const struct device *port, gpio_port_pins_t pins,
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| /Zephyr-Core-2.7.6/include/drivers/ |
| D | gpio.h | 81 * The `GPIO_INT_*` flags are used to specify how input GPIO pins will trigger
216 * The drive strength of individual pins can be configured
269 * @brief Identifies a set of pins associated with a port.
277 * @brief Provides values for a set of pins associated with a port.
466 * @brief Maximum number of pins that are supported by `gpio_port_pins_t`.
476 /* Mask identifying pins supported by the controller.
489 /* Mask identifying pins that are configured as active low.
505 * @param pins Mask of pins that triggers the callback handler
513 gpio_port_pins_t pins);
534 /** A mask of pins the callback is interested in, if 0 the callback
[all …]
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| /Zephyr-Core-2.7.6/boards/arm/teensy4/ |
| D | pinmux.c | 92 /* LPUART6 TX/RX on Teensy-Pins 1/0 */ in teensy4_init()
108 /* LPUART4 TX/RX on Teensy-Pins 8/7 */ in teensy4_init()
124 /* LPUART2 TX/RX on Teensy-Pins 14/15 */ in teensy4_init()
140 /* LPUART3 TX/RX on Teensy-Pins 17/16 */ in teensy4_init()
156 /* LPUART8 TX/RX on Teensy-Pins 20/21 */ in teensy4_init()
172 /* LPUART1 TX/RX on Teensy-Pins 20/21 */ in teensy4_init()
188 /* LPUART7 TX/RX on Teensy-Pins 29/28 */ in teensy4_init()
204 /* LPUART5 TX/RX on Teensy-Pins 35/34 */ in teensy4_init()
220 /* LPI2C3 SCL, SDA on Teensy-Pins 16/17 */ in teensy4_init()
240 /* LPI2C1 SCL, SDA on Teensy-Pins 19/18*/ in teensy4_init()
[all …]
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| /Zephyr-Core-2.7.6/dts/bindings/ethernet/ |
| D | silabs,gecko-ethernet.yaml | 30 description: location of RMII pins, configuration defined as <location>
36 description: location of MDC and MDIO pins, configuration defined as <location>
38 # PHY management pins
49 # RMII interface pins
90 # PHY control pins
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| /Zephyr-Core-2.7.6/dts/arm/atmel/ |
| D | pinctrl_atmel_sam.h | 34 * atmel,pins = < &pio<port> <pin> PERIPH_<perip> >;
47 * atmel,pins = <&pioa 8 PERIPH_a>;
57 * atmel,pins = <&porta 0x4 0x3 >;
70 atmel,pins = < &pio##port pin PERIPH_##periph >; \
77 atmel,pins = < &gpio##port pin PERIPH_##periph >; \
84 atmel,pins = < &port##grouport pin PERIPH_##periph >; \
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| /Zephyr-Core-2.7.6/dts/bindings/pinctrl/ |
| D | atmel,sam-pinctrl.yaml | 8 The Atmel SAM pins implements following pin configuration option:
30 description: Atmel pins
32 "atmel,pins":
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| D | cypress,psoc6-pinctrl.yaml | 8 The Cypress PSoC-6 pins implements following pin configuration option:
33 description: cypress pins
35 "cypress,pins":
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| /Zephyr-Core-2.7.6/soc/arm/nordic_nrf/ |
| D | Kconfig | 42 bool "NFCT pins as GPIOs"
45 Two pins are usually reserved for NFC in SoCs that implement the
49 pins to NFCT mode. Doing this requires UICR erase prior to
52 NFC pins in nRF52 series: P0.09 and P0.10
53 NFC pins in nRF5340: P0.02 and P0.03
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| /Zephyr-Core-2.7.6/include/drivers/adc/ |
| D | lmp90xxx.h | 34 gpio_port_pins_t pins);
37 gpio_port_pins_t pins);
40 gpio_port_pins_t pins);
|
