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11 /*! @brief This abstract layer is to unify the PHY interface in SDK, let application12 * use one set of PHY interfaces. The data structures are applicable to different20 /*! @note The following PHY registers are the IEEE802.3 standard definition, same register and bit …23 /*! @brief Defines the IEEE802.3 standard PHY registers. */24 #define PHY_BASICCONTROL_REG (0x00U) /*!< The PHY basic control register. */25 #define PHY_BASICSTATUS_REG (0x01U) /*!< The PHY basic status register. */26 #define PHY_ID1_REG (0x02U) /*!< The PHY ID one register. */27 #define PHY_ID2_REG (0x03U) /*!< The PHY ID two register. */28 #define PHY_AUTONEG_ADVERTISE_REG (0x04U) /*!< The PHY auto-negotiate advertise register. */29 #define PHY_AUTONEG_LINKPARTNER_REG (0x05U) /*!< The PHY auto negotiation link partner ability regi…[all …]
22 /*! @brief PHY driver version */25 /*! @brief Defines the PHY registers. */26 #define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */27 #define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */28 #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */29 #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */30 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */31 #define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */32 #define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */34 #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/[all …]
22 /*! @brief PHY driver version */25 /*! @brief Defines the PHY registers. */26 #define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */27 #define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */28 #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */29 #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */30 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */31 #define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY control two register. */33 #define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/36 #define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */[all …]
8 * PHY RTL8201 driver change log35 /*! @brief PHY driver version */38 /*! @brief PHY operations structure. */58 * @name PHY Driver63 * @brief Initializes PHY.64 * This function initializes PHY.66 * @param handle PHY device handle.67 * @param config PHY configuration.68 * @retval kStatus_Success PHY initialization succeeds69 * @retval kStatus_Fail PHY initialization fails[all …]
8 * PHY KSZ8081 driver change log35 /*! @brief PHY driver version */44 /*! @brief PHY operations structure. */56 * @name PHY Driver61 * @brief Initializes PHY.62 * This function initializes PHY.64 * @param handle PHY device handle.66 * @retval kStatus_Success PHY initialization succeeds67 * @retval kStatus_Fail PHY initialization fails68 * @retval kStatus_Timeout PHY MDIO visit time out[all …]
13 /*! @brief Defines the PHY KSZ8081 vendor defined registers. */14 #define PHY_INTR_CONTROL_STATUS_REG (0x1BU) /*!< The PHY interrupt control/status register. */15 #define PHY_CONTROL1_REG (0x1EU) /*!< The PHY control one register. */16 #define PHY_CONTROL2_REG (0x1FU) /*!< The PHY control two register. */18 /*! @brief Defines the PHY KSZ8081 ID number. */19 #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1 */22 #define PHY_INTR_CONTROL_STATUS_LINK_UP_MASK ((uint16_t)0x0100U) /*!< The PHY link up interrupt m…23 #define PHY_INTR_CONTROL_STATUS_LINK_DOWN_MASK ((uint16_t)0x0400U) /*!< The PHY link down interrupt…26 #define PHY_CTL2_REMOTELOOP_MASK ((uint16_t)0x0004U) /*!< The PHY remote loopback mask. */27 #define PHY_CTL2_REFCLK_SELECT_MASK ((uint16_t)0x0080U) /*!< The PHY RMII reference clock select. */[all …]
8 * PHY RTL8211F driver change log35 /*! @brief PHY driver version */55 * @name PHY Driver60 * @brief Initializes PHY.61 * This function initializes PHY.63 * @param handle PHY device handle.64 * @param config PHY configuration.65 * @retval kStatus_Success PHY initialization succeeds66 * @retval kStatus_Fail PHY initialization fails67 * @retval kStatus_Timeout PHY MDIO visit time out[all …]
13 /*! @brief Defines the PHY RTL8211F vendor defined registers. */14 #define PHY_SPECIFIC_STATUS_REG (0x1AU) /*!< The PHY specific status register. */15 #define PHY_PAGE_SELECT_REG (0x1FU) /*!< The PHY page select register. */17 /*! @brief Defines the PHY RTL8211F ID number. */18 #define PHY_CONTROL_ID1 (0x001CU) /*!< The PHY ID1 . */21 #define PHY_INER_LINKSTATUS_CHANGE_MASK ((uint16_t)0x0010U) /*!< The PHY link status change interru…24 #define PHY_SSTATUS_LINKSTATUS_MASK ((uint16_t)0x0004U) /*!< The PHY link status mask. */25 #define PHY_SSTATUS_LINKSPEED_MASK ((uint16_t)0x0030U) /*!< The PHY link speed mask. */26 #define PHY_SSTATUS_LINKDUPLEX_MASK ((uint16_t)0x0008U) /*!< The PHY link duplex mask. */29 /*! @brief Defines the PHY RTL8211F extra page and the registers in specified page. */[all …]
8 * PHY AQR113C driver change log35 /*! @brief PHY driver version */55 * @name PHY Driver60 * @brief Initializes PHY.61 * This function initializes PHY.63 * @param handle PHY device handle.64 * @param config PHY configuration.65 * @retval kStatus_Success PHY initialization succeeds66 * @retval kStatus_Fail PHY initialization fails67 * @retval kStatus_Timeout PHY MDIO visit time out[all …]
9 * PHY AR8031 driver change log36 /*! @brief PHY driver version */39 /*! @brief PHY resource structure. */46 /*! @brief PHY operations structure. */58 * @name PHY Driver63 * @brief Initializes PHY.64 * This function initializes PHY.66 * @param handle PHY device handle.68 * @retval kStatus_Success PHY initialization succeeds69 * @retval kStatus_Fail PHY initialization fails[all …]
14 /*! @brief Defines the PHY AR8031 vendor defined registers. */15 #define PHY_SPECIFIC_STATUS_REG 0x11U /*!< The PHY specific status register. */16 #define PHY_COPPERFIBER_STATUS_REG 0x1BU /*!< The PHY copper/fiber status register. */17 #define PHY_DEBUGPORT_ADDR_REG 0x1DU /*!< The PHY Debug port address register.*/18 #define PHY_DEBUGPORT_DATA_REG 0x1EU /*!< The PHY Debug port data register.*/19 #define PHY_CHIP_CFG_REG 0x1FU /*!< The PHY chip configure register. */22 #define PHY_DEBUG_HIBECTL_REG_OFFSET 0x0BU /*!< The PHY Debug register offset 0xB.*/23 #define PHY_DEBUG_EXTLOOP_REG_OFFSET 0x11U /*!< The PHY Debug register offset 0x11.*/25 /*! @brief Defines the PHY AR8031 ID number. */26 #define PHY_CONTROL_ID1 0x004DU /*!< The PHY ID1 is 0x004D. */[all …]
8 * PHY VSC8541 driver change log35 /*! @brief PHY driver version */38 /*! @brief PHY operations structure. */58 * @name PHY Driver63 * @brief Initializes PHY.64 * This function initializes PHY.66 * @param handle PHY device handle.67 * @param config PHY configuration.68 * @retval kStatus_Success PHY initialization succeeds69 * @retval kStatus_Fail PHY initialization fails[all …]
9 * PHY KSZ8041 driver change log36 /*! @brief PHY driver version */39 /*! @brief PHY operations resource. */46 /*! @brief PHY operations method. */58 * @name PHY Driver63 * @brief Initializes PHY.64 * This function initializes PHY.66 * @param handle PHY device handle.68 * @retval kStatus_Success PHY initialization succeeds69 * @retval kStatus_Fail PHY initialization fails[all …]
15 #define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */16 #define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */18 /*! @brief Defines the PHY KSZ8041 ID number. */19 #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1. */22 #define PHY_CTL1_REMOTELOOP_MASK 0x0008U /*!< The PHY remote loopback mask. */23 #define PHY_CTL2_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */24 #define PHY_CTL2_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */25 #define PHY_CTL2_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */26 #define PHY_CTL2_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */31 /*! @brief Defines the PHY resource interface. */[all …]
9 * PHY DP83848 driver change log36 /*! @brief PHY driver version */39 /*! @brief PHY operations structure. */51 * @name PHY Driver56 * @brief Initializes PHY.57 * This function initializes PHY.59 * @param handle PHY device handle.61 * @retval kStatus_Success PHY initialization succeeds62 * @retval kStatus_Fail PHY initialization fails63 * @retval kStatus_PHY_MDIOVisitTimeout PHY MDIO visit time out[all …]
9 * PHY LAN8720A driver change log36 /*! @brief PHY driver version */56 * @name PHY Driver61 * @brief Initializes PHY.62 * This function initializes PHY.64 * @param handle PHY device handle.66 * @retval kStatus_Success PHY initialization succeeds67 * @retval kStatus_Fail PHY initialization fails68 * @retval kStatus_Timeout PHY MDIO visit time out73 * @brief PHY Write function.[all …]
14 /*! @brief Defines the PHY LAN8720A vendor defined registers. */15 #define PHY_CONTROL_REG 0x11U /*!< The PHY control/status register. */16 #define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY special control/status register. */18 /*! @brief Defines the PHY LAN8720A ID number. */19 #define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/25 #define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */26 #define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */27 #define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */28 #define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */29 #define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */[all …]
8 * PHY LAN8741 driver change log35 /*! @brief PHY driver version */55 * @name PHY Driver60 * @brief Initializes PHY.61 * This function initializes PHY.63 * @param handle PHY device handle.65 * @retval kStatus_Success PHY initialization succeeds66 * @retval kStatus_Fail PHY initialization fails67 * @retval kStatus_Timeout PHY MDIO visit time out72 * @brief PHY Write function.[all …]
13 /*! @brief Defines the PHY LAN8741 vendor defined registers. */14 #define PHY_CONTROL_REG 0x11U /*!< The PHY control/status register. */15 #define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY special control/status register. */17 /*! @brief Defines the PHY LAN8741 device ID information. */18 #define PHY_OUI 0x1F0U /*!< The PHY organizationally unique identifier. */19 #define PHY_MODEL_NUM 0x12U /*!< The PHY model number, 6-bit. */26 #define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */27 #define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */28 #define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */29 #define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */[all …]
25 …* Driver supports to access external actual PHY for normal ethernet transmission and internel virt…28 …* wait transmission over through polling busy bit. PHY status automatical check is used to polling…29 * of PHY with hardware at regular intervals.40 * @details IEEE Clause 22/45 MDIO access for PHY45 * @defgroup netc_mdio_phy_status MDIO PHY status module46 * @details Automatically polling to read PHY register with hardware117 * @brief PHY auto status check configuration structure121 …uint16_t interval; /*!< PHY status read interval in units of 1-2 ms. A value of 0 indica…122 bool isC45Used; /*!< PHY status read with Clause 22/45 MDIO access. */123 uint8_t phyOrPortAddr; /*!< MDIO PHY address(Clause 22) / port address(Clause 45). */[all …]
2 * \defgroup PhyInterface PHY Interface4 * The PHY sublayer provides two services: the PHY data service, and the PHY management service inte…5 * The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) ov…6 * The PHY Layer interfaces to the MAC Layer through function calls and function callbacks.7 …function calls, the MAC Layer calls the exposed functions (provided by the PHY Layer) to issue com…40 /*! Number of PHY instances (Only for PHYs which support multiple instances) */45 /*! The PHY task stack size (Only for PHYs which use OS task) */50 /*! The PHY task priority (Only for PHYs which use OS task)51 The PHY Task must have the highest priority! */61 /*! Configure the maximum number of PHY timers/events */[all …]
2 * \defgroup PhyTypes PHY Data Types43 /*! This define is used to set the number of symbols per octet for the current PHY. */49 /*! Maximum number of bytes that the PHY can transmit or receive */53 /*! This define is used to set the duration of the PHY header (PHR) (in symbols) */62 /*! PHY flag that reflects the state of the RxOnWhenIdle function */64 /*! PHY flag that indicate that an automatic RX sequence is ongoing */66 /*! PHY flag that reflects the state of the FP bit of the last ACK frame received */68 /*! PHY flag that reflects the state of the FP bit of the last ACK frame transmitted */72 /*! PHY flag that indicate that the requested TX has been postponed */74 /*! PHY flag that indicate CSL RX: allow multipurpose frames, send Enh-ACKs */[all …]
21 * Project: Ethernet PHY (Physical Transceiver) Driver definitions56 /****** Ethernet PHY Mode *****/68 …E (1UL << 5) ///< Isolate PHY from MII/RMII inter…80 \brief Initialize Ethernet PHY Device.87 \brief De-initialize Ethernet PHY Device.92 \brief Control Ethernet PHY Device Power.104 \brief Set Ethernet PHY Device Operation mode.110 \brief Get Ethernet PHY Device Link state.115 \brief Get Ethernet PHY Device Link information.120 … reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.[all …]
80 /*! @brief Status and interrupt mask of error in phy layer, belongs to interrupt group1. INT_ST0 bi…161 …before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measur…164 …before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measur…167 …before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measur…170 …before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measur…267 /* PHY configuration */268 /*! @brief MIPI DSI D-PHY configuration. */272 …uint8_t tStopState_ByteClk; /*!< Minimum time that the PHY controller stays in stop state before …274 …uint16_t tClkHs2Lp_ByteClk; /*!< Maximum time that the D-PHY clock lane takes to go from high-spe…276 …uint16_t tClkLp2Hs_ByteClk; /*!< Maximum time that the D-PHY clock lane takes to go from low-power[all …]
29 * @brief EHCI PHY get USB phy bass address.31 * This function is used to get USB phy bass address.35 * @retval USB phy bass address.40 * @brief EHCI PHY initialization.42 * This function initializes the EHCI PHY IP.53 * @brief ehci phy initialization for suspend and resume.55 * This function initialize ehci phy IP for suspend and resume.67 * @brief EHCI PHY deinitialization.69 * This function deinitializes the EHCI PHY IP.76 * @brief EHCI PHY disconnect detection enable or disable.[all …]
