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/hal_atmel-3.5.0-3.4.0/asf/sam/include/same70/pio/
Dsame70j19.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
725 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
927 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70j20.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
725 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
927 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70j21.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
725 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
927 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70n19.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
759 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1028 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1053 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70n20.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
759 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1028 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1053 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70n21.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
759 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1028 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1053 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
/hal_atmel-3.5.0-3.4.0/asf/sam/include/samv71/pio/
Dsamv71n19.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
772 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1041 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1066 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71n20.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
405 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
761 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1030 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1055 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71n21.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
405 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
761 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1030 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1055 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71j19.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
405 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
752 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
954 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71j20.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
763 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
965 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71j21.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
416 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
763 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
965 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
/hal_atmel-3.5.0-3.4.0/asf/sam/include/same70b/pio/
Dsame70n19b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
778 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1101 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1126 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70n20b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
778 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1101 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1126 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70n21b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
778 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1101 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1126 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70j19b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
723 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1003 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70j20b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
723 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1003 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70j21b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
723 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1003 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsame70q20b.h114 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
231 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
348 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
888 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
1333 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1795 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1820 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
/hal_atmel-3.5.0-3.4.0/asf/sam/include/samv71b/pio/
Dsamv71n19b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
791 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1114 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1139 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71n20b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
791 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1114 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1139 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71n21b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
791 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1114 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1139 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71j19b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
736 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1016 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71j20b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
736 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1016 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
Dsamv71j21b.h82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */
161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */
240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */
402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
736 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
1016 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …

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