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Searched +full:pcie +full:- +full:ep (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/drivers/pcie/endpoint/
DKconfig.iproc1 # iProc PCIe EP configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Broadcom iProc PCIe EP driver"
9 This option enables Broadcom iProc PCIe EP driver.
14 bool "Re-initialize PCIe MSI/MSIX configurations"
17 bool "Version-2 of iProc PCIe EP controller"
Dpcie_ep_iproc.c4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/pcie/endpoint/pcie_ep.h>
22 const struct iproc_pcie_ep_config *cfg = dev->config; in iproc_pcie_conf_read()
25 pcie_write32(offset, &cfg->base->paxb_config_ind_addr); in iproc_pcie_conf_read()
28 *data = pcie_read32(&cfg->base->paxb_config_ind_data); in iproc_pcie_conf_read()
36 const struct iproc_pcie_ep_config *cfg = dev->config; in iproc_pcie_conf_write()
39 pcie_write32(offset, &cfg->base->paxb_config_ind_addr); in iproc_pcie_conf_write()
42 pcie_write32(data, &cfg->base->paxb_config_ind_data); in iproc_pcie_conf_write()
49 const struct iproc_pcie_ep_config *cfg = dev->config; in iproc_pcie_map_addr()
50 struct iproc_pcie_ep_ctx *ctx = dev->data; in iproc_pcie_map_addr()
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/Zephyr-latest/dts/bindings/pcie/endpoint/
Dbrcm,iproc-pcie-ep.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PCIe EP node
6 compatible: "brcm,iproc-pcie-ep"
14 Register space for the memory mapped PAX(PCIe to AXI bridge) registers,
15 It includes registers to access EP configuration space
16 and to map Host PCIe address to PCIe Outbound memory.
/Zephyr-latest/include/zephyr/drivers/pcie/endpoint/
Dpcie_ep.h4 * @brief Public APIs for the PCIe EP drivers.
8 * SPDX-License-Identifier: Apache-2.0
22 PCIE_OB_ANYMEM, /**< PCIe OB window within any address range */
23 PCIE_OB_LOWMEM, /**< PCIe OB window within 32-bit address range */
24 PCIE_OB_HIGHMEM, /**< PCIe OB window above 32-bit address range */
47 * @brief Callback API for PCIe reset interrupts
50 * interrupt-safe APIS. Registration of callbacks is done via
80 * @brief Read PCIe EP configuration space
82 * @details This API reads EP's own configuration space
95 (const struct pcie_ep_driver_api *)dev->api; in pcie_ep_conf_read()
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/Zephyr-latest/dts/bindings/dma/
Darm,dma-pl330.yaml2 # SPDX-License-Identifier: Apache-2.0
12 compatible = "arm,dma-pl330";
14 dma-channels = <8>;
15 #dma-cells = <1>;
18 If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
19 pcie0_ep: pcie@4e100000 {
20 compatible = "brcm,iproc-pcie-ep";
23 dma-names = "txdma", "rxdma";
25 compatible: "arm,dma-pl330"
27 include: dma-controller.yaml
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Dbrcm,iproc-pax-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
6 include: dma-controller.yaml
8 compatible: brcm,iproc-pax-dma-v1
17 bd-memory:
21 scr-addr-loc:
25 scr-size-loc:
32 pcie-ep:
34 description: Pcie endpoint handle
Dbrcm,iproc-pax-dma-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
6 include: dma-controller.yaml
8 compatible: brcm,iproc-pax-dma-v2
17 bd-memory:
21 scr-addr-loc:
25 scr-size-loc:
32 pcie-ep:
34 description: Pcie endpoint handle
/Zephyr-latest/dts/common/broadcom/
Dviper-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
17 clock-frequency = <25000000>;
18 reg-shift = <2>;
25 clock-frequency = <100000000>;
26 reg-shift = <2>;
31 compatible = "arm,dma-pl330";
34 reg-names = "pl330_regs",
37 dma-channels = <8>;
38 #dma-cells = <1>;
42 pcie {
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/Zephyr-latest/boards/brcm/bcm958402m2/
Dbcm958402m2_bcm58402_m7_defconfig1 # SPDX-License-Identifier: Apache-2.0
16 # Enable PCIe EP
Dbcm958402m2_bcm58402_a72_defconfig1 # SPDX-License-Identifier: Apache-2.0
20 # Enable PCIe EP
/Zephyr-latest/drivers/pcie/host/
Dcontroller.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/pcie/pcie.h>
12 #include <zephyr/drivers/pcie/controller.h>
15 #include <zephyr/drivers/pcie/msi.h>
18 /* arch agnostic PCIe API implementation */
26 LOG_ERR("Failed to get PCIe root complex"); in pcie_conf_read()
39 LOG_ERR("Failed to get PCIe root complex"); in pcie_conf_write()
136 "assigned [%s 0x%lx-0x%lx -> 0x%lx-0x%lx]", in pcie_generic_ctrl_enumerate_bars()
140 bar_bus_addr, bar_bus_addr + bar_size - 1, in pcie_generic_ctrl_enumerate_bars()
141 bar_phys_addr, bar_phys_addr + bar_size - 1); in pcie_generic_ctrl_enumerate_bars()
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