Searched full:pc17 (Results 1 – 25 of 55) sorted by relevance
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96 #define PIN_PC17 ( 81) /**< Pin Number for PC17 */213 #define PIO_PC17 (_U_(1) << 17) /**< PIO Mask for PC17 */330 #define PIO_PC17_IDX ( 81) /**< PIO Index Number for PC17 */1159 #define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: A22 on PC17 mux…1163 #define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: NANDCLE on PC17…1432 #define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: A22 on PC17 mux A*/1436 #define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: NANDCLE on PC17 mu…2163 #define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/2167 #define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mu…
96 #define PIN_PC17 ( 81) /**< Pin Number for PC17 */213 #define PIO_PC17 (_U_(1) << 17) /**< PIO Mask for PC17 */330 #define PIO_PC17_IDX ( 81) /**< PIO Index Number for PC17 */1146 #define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: A22 on PC17 mux…1150 #define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: NANDCLE on PC17…1419 #define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: A22 on PC17 mux A*/1423 #define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: NANDCLE on PC17 mu…2150 #define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/2154 #define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mu…
152 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */153 #define GPIO_PC17 _UL_(1 << 17) /**< \brief GPIO Mask for PC17 */446 #define PIN_PC17A_TC1_A1 _L_(81) /**< \brief TC1 signal: A1 on PC17 mux A */910 #define PIN_PC17D_GLOC_IN6 _L_(81) /**< \brief GLOC signal: IN6 on PC17 mux D */1273 #define PIN_PC17G_CATB_SENSE18 _L_(81) /**< \brief CATB signal: SENSE18 on PC17 mux G */1406 #define PIN_PC17F_LCDCA_SEG2 _L_(81) /**< \brief LCDCA signal: SEG2 on PC17 mux F */
162 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */163 #define GPIO_PC17 _UL_(1 << 17) /**< \brief GPIO Mask for PC17 */496 #define PIN_PC17A_TC1_A1 _L_(81) /**< \brief TC1 signal: A1 on PC17 mux A */992 #define PIN_PC17D_GLOC_IN6 _L_(81) /**< \brief GLOC signal: IN6 on PC17 mux D */1403 #define PIN_PC17G_CATB_SENSE18 _L_(81) /**< \brief CATB signal: SENSE18 on PC17 mux G */
175 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */176 #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */386 #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */740 #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */1043 #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */1413 #define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */1546 #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */1924 #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
185 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */186 #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */427 #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */866 #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */1221 #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */1651 #define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */1784 #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */2190 #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
175 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */176 #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */386 #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */740 #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */1043 #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */1379 #define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */1512 #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */1890 #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
175 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */176 #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */386 #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */740 #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */1043 #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */1423 #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */1801 #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
185 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */186 #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */427 #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */866 #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */1221 #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */1653 #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */2059 #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
175 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */176 #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */386 #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */740 #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */1043 #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */1457 #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */1835 #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
446 pc17:
