| /Zephyr-Core-3.5.0/tests/subsys/portability/cmsis_rtos_v1/src/ |
| D | timer.c | 4 * SPDX-License-Identifier: Apache-2.0
28 TC_PRINT("oneshot_callback (Timer %d) = %d\n", in Timer1_Callback()
37 TC_PRINT("periodic_callback (Timer %d) = %d\n", in Timer2_Callback()
50 /* Create one-shot timer */ in ZTEST()
53 zassert_true(id1 != NULL, "error creating one-shot timer"); in ZTEST()
55 /* Stop the timer before start */ in ZTEST()
57 zassert_true(status == osErrorResource, "error while stopping non-active timer"); in ZTEST()
61 zassert_true(status == osOK, "error starting one-shot timer"); in ZTEST()
63 /* Timer should fire only once if setup in one shot in ZTEST()
64 * mode. Wait for 3 times the one-shot time to see in ZTEST()
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| /Zephyr-Core-3.5.0/tests/subsys/portability/cmsis_rtos_v2/src/ |
| D | timer.c | 4 * SPDX-License-Identifier: Apache-2.0
29 TC_PRINT("oneshot_callback (Timer %d) = %d\n", in Timer1_Callback()
38 TC_PRINT("periodic_callback (Timer %d) = %d\n", in Timer2_Callback()
52 /* Create one-shot timer */ in ZTEST()
55 zassert_true(id1 != NULL, "error creating one-shot timer"); in ZTEST()
59 "Error getting Timer name"); in ZTEST()
61 /* Stop the timer before start */ in ZTEST()
64 "error while stopping non-active timer"); in ZTEST()
68 zassert_true(status == osOK, "error starting one-shot timer"); in ZTEST()
70 zassert_equal(osTimerIsRunning(id1), 1, "Error: Timer not running"); in ZTEST()
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| /Zephyr-Core-3.5.0/tests/kernel/timer/starve/ |
| D | README.txt | 1 Title: Timer Starvation test
3 The purpose of the test is to detect whether the timer implementation
4 correctly handles situations where only one timeout is present, and that
6 some implementations this may prevent the timer interrupt handler from
13 and the tick rate. By default the test passes if one hour passes
17 hardware timer counter, a timer driver internal calculation of
20 For example a system that uses a 32768-Hz internal timer counter with
21 24-bit resolution and determines elapsed time by a 24-bit unsigned
22 difference between the current and last-recorded counter value will fail
26 Systems that use a 32-bit counter of 80 MHz ticks would fail after
|
| /Zephyr-Core-3.5.0/doc/kernel/services/timing/ |
| D | timers.rst | 6 A :dfn:`timer` is a kernel object that measures the passage of time
7 using the kernel's system clock. When a timer's specified time limit
8 is reached it can perform an application-defined action,
19 Any number of timers can be defined (limited only by available RAM). Each timer
22 A timer has the following key properties:
24 * A **duration** specifying the time interval before the timer
28 * A **period** specifying the time interval between all timer
29 expirations after the first one, also a ``k_timeout_t``. It must be
30 non-negative. A period of ``K_NO_WAIT`` (i.e. zero) or
31 ``K_FOREVER`` means that the timer is a one shot timer that stops
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| D | clocks.rst | 46 ----------
66 word, these conversions expand to a 2-4 operation sequence, requiring
67 full precision only where actually required and requested.
102 an opaque struct type that must be initialized using one of a family
113 within another timer's callback will always be calculated with a precise offset
114 to the firing timer. It is thereby possible to fire at regular intervals without
127 being 32 bits. Large uptime counts in non-tick units will experience
129 timing-sensitive applications with long uptimes will be configured to
142 -------------
146 a double-linked list, with an attendant delta count in ticks from the
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| /Zephyr-Core-3.5.0/dts/bindings/rtc/ |
| D | xlnx,xps-timer-1.00.a.yaml | 1 description: Xilinx AXI Timer IP node
3 compatible: "xlnx,xps-timer-1.00.a"
8 # https://github.com/Xilinx/meta-xilinx
11 clock-frequency:
14 xlnx,count-width:
18 - 8
19 - 16
20 - 32
22 Individual timer/counter width in bits.
24 xlnx,gen0-assert:
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| /Zephyr-Core-3.5.0/samples/boards/esp32/deep_sleep/ |
| D | README.rst | 1 .. _esp32-deep-sleep-sample:
14 make use of that pre-configured wake up source to bring the system back again.
18 1. ``Timer``: An RTC timer that can be programmed to trigger a wake up after
21 uses GPIO2 and GPIO4 to trigger a wake up with any one of the two pins are
23 3. ``GPIO``: Only supported by some Espressif SoCs, in the case of ESP32-C3
24 GPIOS0~5 can be used as wake-up sources.
26 In this demo, Timer is the only wake-up source that cannot be disabled via a
27 Kconfig option. The target SoC will always repeat the following: enable Timer
28 as wake-up source, deep sleep for 20 seconds, wake up.
35 only ``Timer`` is used as wakeup source.
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| /Zephyr-Core-3.5.0/drivers/watchdog/ |
| D | Kconfig.it8xxx2 | 2 # SPDX-License-Identifier: Apache-2.0
5 bool "ITE it8xxx2 Watchdog Timer (WDT) driver"
9 This option enables the Watchdog Timer driver for ITE it8xxx2.
10 This driver supports only one channel that id is 0 and 16-bits
26 Once warning timer triggered, if watchdog timer isn't reloaded,
27 then we will reduce interval of warning timer to 30ms to print
|
| /Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/ |
| D | loapic.h | 1 /* loapic.h - public LOAPIC APIs */
6 * SPDX-License-Identifier: Apache-2.0
27 #define LOAPIC_ISR 0x100 /* In-service Reg */
33 #define LOAPIC_TIMER 0x320 /* LVT (Timer) */
39 #define LOAPIC_TIMER_ICR 0x380 /* Timer Initial Count Reg */
40 #define LOAPIC_TIMER_CCR 0x390 /* Timer Current Count Reg */
41 #define LOAPIC_TIMER_CONFIG 0x3e0 /* Timer Divide Config Reg */
42 #define LOAPIC_SELF_IPI 0x3f0 /* Self IPI Reg, only support in X2APIC mode */
70 * @brief Read 64-bit value from the local APIC in x2APIC mode.
81 * @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
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| /Zephyr-Core-3.5.0/dts/bindings/display/ |
| D | nordic,nrf-led-matrix.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-led-matrix"
8 include: display-controller.yaml
11 row-gpios:
12 type: phandle-array
17 col-gpios:
18 type: phandle-array
23 pixel-mapping:
24 type: uint8-array
29 array corresponds to one pixel of the matrix and specifies the row
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/pwm/boards/ |
| D | arty_a7_arm_designstart_m1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "xlnx,xps-timer-1.00.a-pwm";
11 interrupt-parent = <&nvic>;
13 clock-frequency = <100000000>;
14 xlnx,count-width = <0x20>;
15 xlnx,gen0-assert = <0x1>;
16 xlnx,gen1-assert = <0x1>;
17 xlnx,one-timer-only = <0x0>;
18 xlnx,trig0-assert = <0x1>;
19 xlnx,trig1-assert = <0x0>;
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/counter/boards/ |
| D | arty_a7_arm_designstart_m1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "xlnx,xps-timer-1.00.a";
11 interrupt-parent = <&nvic>;
13 clock-frequency = <100000000>;
14 xlnx,count-width = <0x20>;
15 xlnx,gen0-assert = <0x1>;
16 xlnx,gen1-assert = <0x1>;
17 xlnx,one-timer-only = <0x0>;
18 xlnx,trig0-assert = <0x1>;
19 xlnx,trig1-assert = <0x1>;
|
| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | Kconfig.nrfx | 3 # Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
36 in RAM, because EasyDMA in UARTE peripherals can only transfer data
39 # ----------------- port 0 -----------------
87 Hardware RX byte counting requires timer instance and one PPI channel
96 power consumption. It is only feasible if receiver is not always on.
99 int "Timer instance"
113 # ----------------- port 1 -----------------
159 Hardware RX byte counting requires timer instance and one PPI channel
167 power consumption. It is only feasible if receiver is not always on.
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| /Zephyr-Core-3.5.0/drivers/timer/ |
| D | mchp_xec_rtos_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/timer/system_timer.h>
18 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");
20 "XEC RTOS timer HW frequency is fixed at 32768");
25 /* Enable feature to halt timer on JTAG/SWD CPU halt */
35 * This driver enables the Microchip XEC 32KHz based RTOS timer as the Zephyr
36 * system timer. It supports both legacy ("tickful") mode as well as
37 * TICKLESS_KERNEL. The XEC RTOS timer is a down counter with a fixed
39 * timer driver.
49 * program a periodic timer at this fast rate.
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| D | altera_avalon_timer_hal.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/timer/system_timer.h>
18 * one only requires the driver to track ticks since the last announce
19 * call. Implement the new call in terms of the old one on legacy
53 * use a timer instance for both the system clock and timestamps in sys_clock_cycle_get_32()
58 * to reset to the next interval before the timer interrupt is in sys_clock_cycle_get_32()
64 * a second timer peripheral instance that is configured to in sys_clock_cycle_get_32()
65 * count down from some large initial 64-bit value. This in sys_clock_cycle_get_32()
|
| D | ite_it8xxx2_timer.c | 3 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/timer/system_timer.h>
10 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
17 LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
20 "ITE RTOS timer HW frequency is fixed at 32768Hz");
22 /* Event timer configurations */
26 /* Event timer max count is 512 sec (base on clock source 32768Hz) */
29 /* Busy wait low timer configurations */
34 /* Busy wait high timer configurations */
38 /* Busy wait high timer max count is 71.58min (base on clock source 1MHz) */
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| D | gecko_burtc_timer.c | 8 * SPDX-License-Identifier: Apache-2.0
15 * @brief SiLabs Gecko BURTC-based sys_clock driver
22 #include <zephyr/drivers/timer/system_timer.h>
37 /* Maximum time interval between timer interrupts (in hw_cycles) */
56 * should write hw_cycles timer clock frequency upon init
72 /* Set to true when timer is initialized */
84 /* NOTE: this is the only place where g_last_count is modified, in burtc_isr()
85 * so we don't need to do make the whole read-and-modify atomic, just in burtc_isr()
91 uint32_t unannounced = (curr - prev) / g_cyc_per_tick; in burtc_isr()
100 * announce the very next tick - in that case we skip one and in burtc_isr()
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| D | apic_timer.c | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/timer/system_timer.h>
13 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
18 * This driver enables the local APIC as the Zephyr system timer. It supports
20 * work with any APIC that has the ARAT "always running APIC timer" feature
23 * (Ultimately systems with invariant TSCs should use a TSC-based driver,
24 * and the TSC-related parts should be stripped from this implementation.)
28 * CONFIG_APIC_TIMER=y enables this timer driver.
29 * CONFIG_APIC_TIMER_IRQ=<irq> which IRQ to configure for the timer.
33 * by the local APIC timer block (before it gets to the timer divider).
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/timer/ |
| D | system_timer.h | 5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Timer driver API
12 * Declare API implemented by system timer driver and used by kernel components.
39 * is that one tick announcement should occur within one tick BEFORE
47 * indicating that no future timer interrupts are expected or required
59 * ticks and real-world time must be correct.
76 * @brief Timer idle exit notification
78 * This notifies the timer driver that the system is exiting the idle
79 * and allows it to do whatever bookkeeping is needed to restore timer
82 * @note Legacy timer drivers also use this opportunity to call back
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| /Zephyr-Core-3.5.0/doc/services/task_wdt/ |
| D | index.rst | 9 Many microcontrollers feature a hardware watchdog timer peripheral. Its purpose
11 malfunctions. Once initialized, the watchdog timer has to be restarted ("fed")
16 In real-time operating systems with multiple tasks running in parallel, a
18 only one task. This software watchdog based on kernel timers provides a method
24 The task watchdog uses a kernel timer as its backend. If configured properly,
25 the timer ISR is never actually called during normal operation, as the timer is
|
| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | espressif,esp32-ledc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
14 pinctrl-0 = <&ledc0_default>;
15 pinctrl-names = "default";
18 The 'ledc0_default' node state is defined in <board>-pinctrl.dtsi.
25 output-enable;
29 If another GPIO mapping is desired, check if <board>-pinctrl.dtsi already have it defined,
33 https://github.com/zephyrproject-rtos/hal_espressif/tree/zephyr/include/dt-bindings/pinctrl
46 output-enable;
55 pinctrl-0 = <&ledc0_custom>;
56 pinctrl-names = "default";
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_stm32.c | 6 * SPDX-License-Identifier: Apache-2.0
24 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
31 /* L0 series MCUs only have 16-bit timers and don't have below macro defined */
39 * @brief Capture state when in 4-channel support mode
65 /* only used when four_channel_capture_support */
71 * This is not the case when using four-channel-support.
79 /** Timer clock (Hz). */
90 TIM_TypeDef *timer; member
101 /** Maximum number of timer channels : some stm32 soc have 6 else only 4 */
131 /** Maximum number of complemented timer channels is ARRAY_SIZE(ch2ll_n)*/
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| D | pwm_nrf_sw.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/gpio.h>
30 "Only clock-prescaler = <0> is supported when used with RTC");
39 /* One compare channel is needed to set the PWM period, hence +1. */
50 /* When RTC is used, one more PPI task endpoint is required for clearing
51 * the counter, so when FORK feature is not available, one more PPI channel
63 NRF_TIMER_Type *timer; member
81 return config->rtc; in pwm_config_rtc()
90 return config->timer; in pwm_config_timer()
110 (data->pulse_cycles[i] != 0U) && in pwm_period_check()
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| /Zephyr-Core-3.5.0/tests/kernel/timer/timer_api/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
20 #define WITHIN_ERROR(var, target, epsilon) (llabs((int64_t) ((target) - (var))) <= (epsilon))
22 /* ms can be converted precisely to ticks only when a ms is exactly
32 /* On Nordic SOCs one or both of the tick and busy-wait clocks may
33 * derive from sources that have slews that sum to +/- 13%.
43 * remaining time for a partially elapsed timer in ticks will be
52 static void duration_expire(struct k_timer *timer);
53 static void duration_stop(struct k_timer *timer);
55 /** TESTPOINT: init timer via K_TIMER_DEFINE */
99 * one-ticks deltas (NOT one two-tick delta!) in interval_check()
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| /Zephyr-Core-3.5.0/drivers/adc/ |
| D | adc_context.h | 5 * SPDX-License-Identifier: Apache-2.0
22 * - adc_context_start_sampling() that will be called when a sampling (of one
24 * - adc_context_update_buffer_pointer() that will be called when the sample
33 * If a given driver uses some dedicated hardware timer to trigger consecutive
36 * this module that utilize a standard kernel timer.
58 struct k_timer timer; member
77 ._ctx_name.timer = Z_TIMER_INITIALIZER(_data._ctx_name.timer, \
95 k_timer_init(&ctx->timer, adc_context_on_timer_expired, NULL); in adc_context_init()
97 k_sem_init(&ctx->lock, 0, 1); in adc_context_init()
98 k_sem_init(&ctx->sync, 0, 1); in adc_context_init()
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