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/Zephyr-latest/boards/snps/nsim/arc_classic/doc/
Dindex.rst1 .. zephyr:board:: nsim
7 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
24 * ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
25 * ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options a…
27 * ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
28 * ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
29 * ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
30 * ``nsim/nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template
31 * ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
[all …]
/Zephyr-latest/tests/kernel/timer/timer_api/
Dtestcase.yaml13 - nsim/nsim_em
14 - nsim/nsim_em7d_v22
15 - nsim/nsim_hs
16 - nsim/nsim_hs/mpuv6
17 - nsim/nsim_hs5x
18 - nsim/nsim_hs6x
25 - nsim/nsim_em
/Zephyr-latest/boards/snps/nsim/arc_classic/
Dboard.cmake2 set(SUPPORTED_EMU_PLATFORMS nsim)
8 board_set_flasher_ifnset(arc-nsim)
9 board_set_debugger_ifnset(arc-nsim)
12 board_runner_args(arc-nsim "--props=${NSIM_PROPS}")
15 string(REPLACE "nsim" "mdb" MDB_ARGS "${NSIM_BASE_FILENAME}.args")
17 board_runner_args(mdb-nsim "--cores=${CONFIG_MP_MAX_NUM_CPUS}" "--nsim_args=${MDB_ARGS}")
20 board_finalize_runner_args(arc-nsim)
21 include(${ZEPHYR_BASE}/boards/common/mdb-nsim.board.cmake)
Dnsim_nsim_vpx5.yaml1 identifier: nsim/nsim_vpx5
2 name: VPX5 nSIM simulator
5 - name: nsim
Dnsim_nsim_em.yaml1 identifier: nsim/nsim_em
2 name: EM Nsim simulator
5 - name: nsim
Dnsim_nsim_em11d.yaml1 identifier: nsim/nsim_em11d
2 name: EM11D Nsim simulator
5 - name: nsim
Dnsim_nsim_em7d_v22.yaml1 identifier: nsim/nsim_em7d_v22
2 name: EM nSIM simulator (EM7D_v22)
5 - name: nsim
Dnsim_nsim_hs.yaml1 identifier: nsim/nsim_hs
2 name: HS nSIM simulator
5 - name: nsim
Dnsim_nsim_hs5x.yaml1 identifier: nsim/nsim_hs5x
2 name: HS5x nSIM simulator
5 - name: nsim
Dnsim_nsim_hs6x.yaml1 identifier: nsim/nsim_hs6x
2 name: HS6x nSIM simulator
5 - name: nsim
Dnsim_nsim_hs_hostlink.yaml1 identifier: nsim/nsim_hs/hostlink
2 name: HS3x nSIM simulator
5 - name: nsim
Dnsim_nsim_sem.yaml1 identifier: nsim/nsim_sem
2 name: SEM nSIM simulator
6 - name: nsim
Dnsim_nsim_hs_sram.yaml1 identifier: nsim/nsim_hs/sram
2 name: HS nSIM simulator (SRAM)
5 - name: nsim
Dnsim_nsim_hs_flash_xip.yaml1 identifier: nsim/nsim_hs/flash_xip
2 name: HS nSIM simulator (FLASH XIP)
5 - name: nsim
Dnsim_nsim_sem_mpu_stack_guard.yaml1 identifier: nsim/nsim_sem/mpu_stack_guard
2 name: SEM nSIM simulator (stack guard)
6 - name: nsim
/Zephyr-latest/tests/lib/multi_heap/
Dtestcase.yaml13 - nsim/nsim_em
14 - nsim/nsim_em7d_v22
15 - nsim/nsim_hs
16 - nsim/nsim_hs/mpuv6
17 - nsim/nsim_hs5x
18 - nsim/nsim_hs6x
/Zephyr-latest/tests/kernel/threads/no-multithreading/
Dtestcase.yaml13 - nsim/nsim_em
14 - nsim/nsim_em7d_v22
15 - nsim/nsim_hs
16 - nsim/nsim_hs/mpuv6
17 - nsim/nsim_hs5x
18 - nsim/nsim_hs6x
/Zephyr-latest/tests/kernel/fatal/no-multithreading/
Dtestcase.yaml10 - nsim/nsim_em
11 - nsim/nsim_em7d_v22
12 - nsim/nsim_hs
13 - nsim/nsim_hs/mpuv6
14 - nsim/nsim_hs5x
15 - nsim/nsim_hs6x
18 - nsim/nsim_em
/Zephyr-latest/tests/kernel/mem_slab/mslab_api/
Dtestcase.yaml13 - nsim/nsim_em
14 - nsim/nsim_em7d_v22
15 - nsim/nsim_hs
16 - nsim/nsim_hs/mpuv6
17 - nsim/nsim_hs5x
18 - nsim/nsim_hs6x
/Zephyr-latest/boards/snps/nsim/arc_v/
Dboard.cmake3 set(SUPPORTED_EMU_PLATFORMS nsim)
8 board_set_flasher_ifnset(arc-nsim)
9 board_set_debugger_ifnset(arc-nsim)
12 board_runner_args(arc-nsim "--props=${NSIM_PROPS}")
14 board_finalize_runner_args(arc-nsim)
15 include(${ZEPHYR_BASE}/boards/common/mdb-nsim.board.cmake)
/Zephyr-latest/cmake/emu/
Dnsim.cmake2 if("${BOARD_DEBUG_RUNNER}" STREQUAL "mdb-nsim" OR "${BOARD_FLASH_RUNNER}" STREQUAL "mdb-nsim")
3 # mdb is required to run nsim multicore targets
27 …list(APPEND MDB_OPTIONS ${MDB_BASIC_OPTIONS} -nsim @${BOARD_DIR}/support/${MDB_ARGS} ${APPLICATION…
32 …list(APPEND MDB_OPTIONS && ${MDB} ${MDB_BASIC_OPTIONS} -nsim @${BOARD_DIR}/support/${MDB_ARGS} -ru…
47 NSIM
53 ${NSIM}
59 …COMMENT "nSIM COMMAND: ${NSIM} -propsfile ${BOARD_DIR}/support/${NSIM_PROPS} ${APPLICATION_BINARY_…
65 ${NSIM}
/Zephyr-latest/scripts/pylib/twister/twisterlib/
Dconstants.py8 "mdb-nsim",
9 "nsim",
20 SUPPORTED_SIMS_WITH_EXEC = ['nsim', 'mdb-nsim', 'renode', 'tsim', 'native', 'simics', 'custom']
/Zephyr-latest/boards/snps/nsim/arc_v/doc/
Dindex.rst7 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
20 files in :zephyr_file:`boards/snps/nsim/arc_v/support/` directory to understand
24 All nSIM targets are used for demo and testing purposes. They are not meant to
34 either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required.
43 I.e. for the ``nsim_arc_v/rmx100`` board we can check :zephyr_file:`boards/snps/nsim/arc_v/nsim_arc…
62 nSIM, for example, with the :zephyr:code-sample:`synchronization` sample:
71 nSIM, and display the following console output:
100 Debugging on nSIM via GDB is only supported on single-core targets (which use standalone
101 nSIM).
104 The normal ``west debug`` command won't work for debugging applications using nsim boards
[all …]
/Zephyr-latest/scripts/west_commands/runners/
Dnsim.py17 '''Runner front-end for the ARC nSIM.'''
41 return 'arc-nsim'
50 help='nsim gdb port, defaults to 3333')
52 help='nsim props file, defaults to nsim.props')
63 kwargs['nsim-cfg'] = path.join(self.cfg.board_dir, 'support',
74 config = kwargs['nsim-cfg']
83 config = kwargs['nsim-cfg']
96 config = kwargs['nsim-cfg']
/Zephyr-latest/boards/common/
Dmdb-nsim.board.cmake3 board_set_flasher_ifnset(mdb-nsim)
4 board_set_debugger_ifnset(mdb-nsim)
5 board_finalize_runner_args(mdb-nsim)

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