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/Zephyr-latest/subsys/fs/nvs/
DKconfig1 # Non-volatile Storage NVS
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Non-volatile Storage"
12 Enable support of Non-volatile Storage.
17 bool "Non-volatile Storage lookup cache"
19 Enable Non-volatile Storage cache, used to reduce the NVS data lookup
24 int "Non-volatile Storage lookup cache size"
29 Number of entries in Non-volatile Storage lookup cache.
33 bool "Non-volatile Storage CRC protection on the data"
35 Enable a CRC-32 on the data part of each NVS element.
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/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_context.h7 * Copyright (c) 2011-2014 Wind River Systems, Inc.
9 * SPDX-License-Identifier: Apache-2.0
24 * that is, it may evaluate to a non-zero value.
38 * specific IA-32 processor, but for now only the Pentium4 is supported:
40 * 8 x 80 bit floating point registers (ST[0] -> ST[7])
41 * 8 x 128 bit XMM registers (XMM[0] -> XMM[7])
43 * All these registers are considered volatile across a function invocation.
55 struct xmm_register xmm[8]; /* XMM[0] -> XMM[7] */
56 struct fp_register st[8]; /* ST[0] -> ST[7] */
60 /* No non-volatile floating point registers */
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/Zephyr-latest/modules/canopennode/
Dcanopennode.h4 * SPDX-License-Identifier: Apache-2.0
53 * CANOPEN_STORAGE_ROM to non-volatile storage when a CANopen SDO
55 * object dictionary index 0x1010 sub-index 1.
59 * non-volatile storage when a CANopen SDO client writes 0x64616F6C
61 * 0x1011 sub-index 1.
68 * never saved to non-volatile storage.
76 * @brief Save CANopen object dictionary entries to non-volatile storage.
78 * Save object dictionary entries of a given type to non-volatile
88 * @brief Erase CANopen object dictionary entries from non-volatile storage.
90 * Erase object dictionary entries of a given type from non-volatile
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/Zephyr-latest/include/zephyr/fs/
Dnvs.h1 /* NVS: non volatile storage in flash
5 * SPDX-License-Identifier: Apache-2.0
20 * @brief Non-volatile Storage (NVS)
21 * @defgroup nvs Non-volatile Storage (NVS)
30 * @brief Non-volatile Storage Data Structures
31 * @defgroup nvs_data_structures Non-volatile Storage Data Structures
37 * @brief Non-volatile Storage File system structure
44 * - high 2 bytes correspond to the sector
45 * - low 2 bytes are the offset in the sector
50 /** File system is split into sectors, each sector must be multiple of erase-block-size */
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/Zephyr-latest/include/zephyr/arch/common/
Dsys_io.h5 * SPDX-License-Identifier: Apache-2.0
8 /* Memory mapped registers I/O functions in non-arch-specific C code */
25 return *(volatile uint8_t *)addr; in sys_read8()
30 *(volatile uint8_t *)addr = data; in sys_write8()
35 return *(volatile uint16_t *)addr; in sys_read16()
40 *(volatile uint16_t *)addr = data; in sys_write16()
45 return *(volatile uint32_t *)addr; in sys_read32()
50 *(volatile uint32_t *)addr = data; in sys_write32()
55 return *(volatile uint64_t *)addr; in sys_read64()
60 *(volatile uint64_t *)addr = data; in sys_write64()
Dsys_bitops.h6 * SPDX-License-Identifier: Apache-2.0
9 /* Memory bits manipulation functions in non-arch-specific C code */
26 uint32_t temp = *(volatile uint32_t *)addr; in sys_set_bit()
28 *(volatile uint32_t *)addr = temp | (1 << bit); in sys_set_bit()
33 uint32_t temp = *(volatile uint32_t *)addr; in sys_clear_bit()
35 *(volatile uint32_t *)addr = temp & ~(1 << bit); in sys_clear_bit()
40 uint32_t temp = *(volatile uint32_t *)addr; in sys_test_bit()
47 uint32_t temp = *(volatile uint32_t *)addr; in sys_set_bits()
49 *(volatile uint32_t *)addr = temp | mask; in sys_set_bits()
54 uint32_t temp = *(volatile uint32_t *)addr; in sys_clear_bits()
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dull_sync_types.h4 * SPDX-License-Identifier: Apache-2.0
21 /* Non-zero when sync is setup. It can be in two sub-stated:
22 * - Waiting for first AUX_SYNC_IND, before sync established was notified to Host.
24 * - sync is already established, node_rx_sync_estab is NULL.
26 uint16_t volatile timeout_reload;
73 /* Not-Null when sync was setup and Controller is waiting for first AUX_SYNC_IND PDU.
87 /* Non-Null when creating sync, reset in ISR context on
89 * cancelling sync create, hence the volatile keyword.
91 struct ll_sync_iso_set *volatile sync_iso;
129 uint16_t volatile timeout_reload; /* Non-zero when sync established */
Dull_scan_types.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
29 /* Non-Null when creating sync, reset in ISR context on
31 * cancelling sync create, hence the volatile keyword.
33 struct ll_sync_set *volatile sync;
42 void *volatile parent;
45 /* TODO - do we need both head and tail? */
75 void *volatile parent;
/Zephyr-latest/arch/arm/include/cortex_m/
Dtz_ns.h4 * SPDX-License-Identifier: Apache-2.0
11 * TrustZone API for Cortex-M CPUs implementing the Security Extension.
44 * r0-r3 unmodified.
47 * r0-r3 unmodified.
50 __asm__ volatile( \
52 __asm__ volatile( \
54 __asm__ volatile( \
56 __asm__ volatile( \
58 "push {r0-r3}\n\t" \
60 "pop {r0-r3}\n\t" \
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/Zephyr-latest/dts/bindings/flash_controller/
Dnordic,nrf51-flash-controller.yaml1 description: Nordic NVMC (Non-Volatile Memory Controller)
3 compatible: "nordic,nrf51-flash-controller"
5 include: flash-controller.yaml
Datmel,sam0-nvmctrl.yaml1 description: Atmel SAM0 NVMC (Non-Volatile Memory Controller)
3 compatible: "atmel,sam0-nvmctrl"
5 include: flash-controller.yaml
8 lock-regions:
Dnordic,nrf52-flash-controller.yaml1 description: Nordic NVMC (Non-Volatile Memory Controller)
3 compatible: "nordic,nrf52-flash-controller"
5 include: flash-controller.yaml
8 partial-erase:
Dnordic,nrf53-flash-controller.yaml1 description: Nordic NVMC (Non-Volatile Memory Controller)
3 compatible: "nordic,nrf53-flash-controller"
5 include: flash-controller.yaml
8 partial-erase:
Dnordic,nrf91-flash-controller.yaml1 description: Nordic NVMC (Non-Volatile Memory Controller)
3 compatible: "nordic,nrf91-flash-controller"
5 include: flash-controller.yaml
8 partial-erase:
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dsys_io.h5 * SPDX-License-Identifier: Apache-2.0
8 /* "Arch" bit manipulation functions in non-arch-specific C code (uses some
31 __asm__ volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr)); in sys_read8()
40 __asm__ volatile("strb %0, [%1]" : : "r" (data), "r" (addr)); in sys_write8()
47 __asm__ volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr)); in sys_read16()
56 __asm__ volatile("strh %0, [%1]" : : "r" (data), "r" (addr)); in sys_write16()
63 __asm__ volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); in sys_read32()
72 __asm__ volatile("str %0, [%1]" : : "r" (data), "r" (addr)); in sys_write32()
79 __asm__ volatile("ldrd %Q0, %R0, [%1]" : "=r" (val) : "r" (addr)); in sys_read64()
/Zephyr-latest/soc/ene/kb1200/reg/
Dfsmbm.h4 * SPDX-License-Identifier: Apache-2.0
14 volatile uint32_t FSMBMCFG; /* Configuration Register */
15 volatile uint8_t FSMBMIE; /* Interrupt Enable Register */
16 volatile uint8_t Reserved0[3];
17 volatile uint8_t FSMBMPF; /* Event Pending Flag Register */
18 volatile uint8_t Reserved1[3];
19 volatile uint8_t FSMBMFRT; /* Protocol Control Register */
20 volatile uint8_t Reserved2[3];
21 volatile uint16_t FSMBMPEC; /* PEC Value Register */
22 volatile uint16_t Reserved3;
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc13xx_cc26xx.h4 * SPDX-License-Identifier: Apache-2.0
6 * References are to the IEEE 802.15.4-2020 standard.
24 /* For O-QPSK the physical and MAC timing symbol rates are the same, see section 12.3.3. */
28 /* PHY PIB attribute phyCcaMode - CCA Mode 3: Carrier sense with energy above threshold, see
29 * section 11.3, table 11-2 and section 10.2.8
40 /* IEEE 802.15.4-2006 MAC PIB attributes (7.4.2)
43 * non-beacon enabled PANs (See IEEE 802.15.4-2006 7.5.6.4.2)
56 #define CC13XX_CC26XX_CPE0_IRQ (INT_RFC_CPE_0 - 16)
57 #define CC13XX_CC26XX_CPE1_IRQ (INT_RFC_CPE_1 - 16)
59 #define CC13XX_CC26XX_RECEIVER_SENSITIVITY -100
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/Zephyr-latest/include/zephyr/arch/arm64/
Dsys_io.h5 * SPDX-License-Identifier: Apache-2.0
8 /* "Arch" bit manipulation functions in non-arch-specific C code (uses some
29 * "volatile pointer" approach compiler might generate instruction with
41 __asm__ volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); in sys_read8()
50 __asm__ volatile("strb %w0, [%1]" : : "r" (data), "r" (addr)); in sys_write8()
57 __asm__ volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); in sys_read16()
66 __asm__ volatile("strh %w0, [%1]" : : "r" (data), "r" (addr)); in sys_write16()
73 __asm__ volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); in sys_read32()
82 __asm__ volatile("str %w0, [%1]" : : "r" (data), "r" (addr)); in sys_write32()
89 __asm__ volatile("ldr %x0, [%1]" : "=r" (val) : "r" (addr)); in sys_read64()
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.c4 * SPDX-License-Identifier: Apache-2.0
69 /** 0: non-vectored 1:vectored */
80 volatile union CLICINTIP INTIP;
81 volatile union CLICINTIE INTIE;
82 volatile union CLICINTATTR INTATTR;
83 volatile uint8_t INTCTRL;
89 #define ECLIC_CFG (*((volatile union CLICCFG *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 0))))
90 #define ECLIC_INFO (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1))))
91 #define ECLIC_MTH (*((volatile union CLICMTH *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 2))))
92 #define ECLIC_CTRL ((volatile struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))
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/Zephyr-latest/tests/kernel/common/src/
Dpow2.c4 * SPDX-License-Identifier: Apache-2.0
22 * @brief Verify compile-time constant results
48 * @brief Verify run-time non-constant results
52 * @details Check if run-time non-constant results are as expected.
53 * Use a volatile variable to prevent compiler optimizations.
59 volatile unsigned int x = test_value; in test_pow2_ceil_x()
/Zephyr-latest/arch/x86/core/ia32/
Dswap.S2 * Copyright (c) 2010-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Kernel swapper code for IA-32
11 * This module implements the arch_swap() routine for the IA-32 architecture.
34 * only the non-volatile integer registers need to be saved in the TCS of the
37 * The X86_THREAD_FLAG_INT and _EXC bits in the k_thread->arch.flags field will
39 * the volatile and non-volatile integer registers need to be restored.
41 * The non-volatile registers need to be scrubbed to ensure they contain no
44 * another via these volatile registers.
54 * point registers. Floating point registers consist of ST0->ST7 (x87 FPU and
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Dfloat.c2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
62 __asm__ volatile( in z_FpAccessDisable()
73 * @brief Save non-integer context information
75 * This routine saves the system's "live" non-integer context into the
82 __asm__ volatile("fnsave (%0);\n\t" in z_do_fp_regs_save()
89 * @brief Save non-integer context information
91 * This routine saves the system's "live" non-integer context into the
98 __asm__ volatile("fxsave (%0);\n\t" in z_do_fp_and_sse_regs_save()
111 __asm__ volatile("fninit\n\t"); in z_do_fp_regs_init()
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/Zephyr-latest/subsys/lorawan/nvm/
DKconfig1 # LoRaWAN Non Volatile Memory configuration options
4 # SPDX-License-Identifier: Apache-2.0
/Zephyr-latest/include/zephyr/arch/x86/ia32/
Dexception.h2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
25 * The exception stack frame includes the volatile registers (EAX, ECX, and
26 * EDX) as well as the 5 non-volatile registers (EDI, ESI, EBX, EBP and ESP).
/Zephyr-latest/subsys/settings/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
8 deserialize state in memory into and from non-volatile memory.
9 It supports several back-ends to store and load serialized data from
15 module-str = settings
19 bool "runtime storage back-end"
21 Enables runtime storage back-end.
34 prompt "Storage back-end"
40 Storage back-end to be used by the settings subsystem.
46 Use FCB as a settings storage back-end.
53 Use a file (on mounted file system) as a settings storage back-end.
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