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/Zephyr-Core-3.5.0/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-Core-3.5.0/drivers/pcie/host/
Dpcie_ecam.c4 * SPDX-License-Identifier: Apache-2.0
24 * - handle prefetchable regions
47 const struct pcie_ctrl_config *cfg = dev->config; in pcie_ecam_init()
48 struct pcie_ecam_data *data = dev->data; in pcie_ecam_init()
52 * Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 : in pcie_ecam_init()
63 * p is 1 if the addressable region is "prefetchable", 0 otherwise in pcie_ecam_init()
64 * t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory), in pcie_ecam_init()
69 * 10 denotes 32-bit-address Memory Space in pcie_ecam_init()
70 * 11 denotes 64-bit-address Memory Space in pcie_ecam_init()
71 * bbbbbbbb is the 8-bit Bus Number in pcie_ecam_init()
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Dcontroller.c4 * SPDX-License-Identifier: Apache-2.0
136 "assigned [%s 0x%lx-0x%lx -> 0x%lx-0x%lx]", in pcie_generic_ctrl_enumerate_bars()
140 bar_bus_addr, bar_bus_addr + bar_size - 1, in pcie_generic_ctrl_enumerate_bars()
141 bar_phys_addr, bar_phys_addr + bar_size - 1); in pcie_generic_ctrl_enumerate_bars()
164 /* Handle only PCI-to-PCI bridge for now */ in pcie_generic_ctrl_enumerate_type1()
209 /* TODO: add support for prefetchable */ in pcie_generic_ctrl_enumerate_type1()
229 bus_number - 1, in pcie_generic_ctrl_post_enumerate_type1()
240 ((bar_base_addr - 1) & 0x0000f000) >> 16, in pcie_generic_ctrl_post_enumerate_type1()
245 ((bar_base_addr - 1) & 0xffff0000) >> 16)); in pcie_generic_ctrl_post_enumerate_type1()
255 (bar_base_addr - 1) >> 16)); in pcie_generic_ctrl_post_enumerate_type1()
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