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/Zephyr-latest/doc/_static/images/
Dlogo-readme-light.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
5 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
29 …-1{fill:#7929d2;}.cls-2{fill:#9454db;}.cls-3{fill:#af7fe4;}.cls-4{fill:url(#linear-gradient);}.cls…
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Dlogo-readme-dark.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
5 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
29 …-1{fill:#7929d2;}.cls-2{fill:#9454db;}.cls-3{fill:#af7fe4;}.cls-4{fill:url(#linear-gradient);}.cls…
31 id="linear-gradient"
39 stop-color="#7929d2"
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49 y1="-1.87884"
55 stop-color="#00aeff"
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Dlogo.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
5 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
29 …-1{fill:#7929d2;}.cls-2{fill:#9454db;}.cls-3{fill:#af7fe4;}.cls-4{fill:url(#linear-gradient);}.cls…
31 id="linear-gradient"
39 stop-color="#7929d2"
42 offset="1"
43 stop-color="#0070c5"
47 id="linear-gradient-2"
49 y1="-1.87884"
55 stop-color="#00aeff"
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/Zephyr-latest/dts/bindings/sdhc/
Dnxp,imx-usdhc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-usdhc"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 data-timeout:
20 read-watermark:
26 write-watermark:
36 Max drive current in mA at 3.3V. A value of zero indicates no maximum
41 pwr-gpios:
42 type: phandle-array
49 cd-gpios:
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/Zephyr-latest/doc/_doxygen/
Dlogo.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
5 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
29 …-1{fill:#7929d2;}.cls-2{fill:#9454db;}.cls-3{fill:#af7fe4;}.cls-4{fill:url(#linear-gradient);}.cls…
31 id="linear-gradient"
39 stop-color="#7929d2"
42 offset="1"
43 stop-color="#0070c5"
47 id="linear-gradient-2"
49 y1="-1.87884"
55 stop-color="#00aeff"
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/Zephyr-latest/scripts/tests/twister_blackbox/
Dtest_output.py4 # SPDX-License-Identifier: Apache-2.0
17 # pylint: disable=no-name-in-module
26 (['-ll', 'DEBUG']),
27 (['-v']),
28 (['-v', '-ll', 'DEBUG']),
29 (['-vv']),
30 (['-vv', '-ll', 'DEBUG']),
47 ('--no-detailed-test-id', False),
48 ('--detailed-test-id', True)
50 ids=['no-detailed-test-id', 'detailed-test-id']
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/Zephyr-latest/dts/bindings/display/
Dsitronix,st7796s.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
12 type: uint8-array
19 type: uint8-array
22 Frame rate control (idle mode / 8 colors). This property sets the
26 type: uint8-array
33 type: uint8-array
40 type: uint8-array
47 type: uint8-array
49 description: Power control parameter 1. Sets AVDDS, AVLCS, and VGHS
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/Zephyr-latest/include/zephyr/drivers/usb_c/
Dusbc_pd.h3 * SPDX-License-Identifier: Apache-2.0
8 * @brief USB-C Power Delivery API used for USB-C drivers
31 * @brief Maximum length of a non-Extended Message in bytes.
32 * See Table 6-75 Value Parameters
39 * See Table 6-75 Value Parameters
51 * See Table 6-75 Value Parameters
57 * @name USB PD 3.1 Rev 1.6, Table 6-70 Counter Parameters
71 * is no response from the remote device (see Section 6.6.6)
79 * @name USB PD 3.1 Rev 1.6, Table 6-68 Time Values
130 * 1) The Port is Attached.
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/Zephyr-latest/boards/native/doc/
Dlayering_natsim.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
7 color-interpolation-filters="sRGB"
12 inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
14 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
17 xmlns:v="http://schemas.microsoft.com/visio/2003/SVGExtensions/"><defs
26 inkscape:document-units="in"
31 inkscape:window-width="2399"
32 inkscape:window-height="1422"
33 inkscape:window-x="161"
34 inkscape:window-y="0"
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Dlayering.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
3 …g/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ev="http://www.w3.org/2001/xml-events"
4 …xmlns:v="http://schemas.microsoft.com/visio/2003/SVGExtensions/" width="6.10236in" height="3.6811i…
5 viewBox="0 0 439.37 265.039" xml:space="preserve" color-interpolation-filters="sRGB" class="st9">
6 <v:documentProperties v:langID="1033" v:metric="true" v:viewMarkup="false">
7 <v:userDefs>
8 <v:ud v:nameU="msvSubprocessMaster" v:prompt="" v:val="VT4(Rectangle)"/>
9 <v:ud v:nameU="msvNoAutoConnect" v:val="VT0(1):26"/>
10 </v:userDefs>
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DZephyr_and_bsim.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
3 …g/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ev="http://www.w3.org/2001/xml-events"
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8 <v:ud v:nameU="msvSubprocessMaster" v:prompt="" v:val="VT4(Rectangle)"/>
9 <v:ud v:nameU="msvNoAutoConnect" v:val="VT0(1):26"/>
10 </v:userDefs>
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/Zephyr-latest/boards/pjrc/teensy4/
Dteensy41.dts4 * SPDX-License-Identifier: Apache-2.0
13 zephyr,flash-controller = &w25q64jvxgim;
18 /delete-node/ &w25q16jvuxim;
22 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
25 compatible = "nxp,imx-flexspi-nor";
26 size = <DT_SIZE_M(8 * 8)>;
28 spi-max-frequency = <DT_FREQ_M(133)>;
30 jedec-id = [ef 70 17];
32 erase-block-size = <4096>;
33 write-block-size = <1>;
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/Zephyr-latest/dts/bindings/gpio/
Darduino-header-r3.yaml3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
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/Zephyr-latest/boards/espressif/esp32s3_eye/doc/
Dindex.rst6 The ESP32-S3-EYE is a small-sized AI development board produced by [Espressif](https://espressif.co…
7 It is based on the [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) SoC.
8 It features a 2-Megapixel camera, an LCD display, and a microphone, which are used for image
9 recognition and audio processing. ESP32-S3-EYE offers plenty of storage, with an 8 MB Octal PSRAM
10 and a 8 MB flash.
15 The ESP32-S3-EYE board consists of two parts: the main board (ESP32-S3-EYE-MB) that integrates the
16 ESP32-S3-WROOM-1 module, camera, SD card slot, digital microphone, USB port, and function buttons;
17 and the sub board (ESP32-S3-EYE-SUB) that contains an LCD display.
21 -------------
23 The block diagram below presents main components of the ESP32-S3-EYE-MB main board (on the left)
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/Zephyr-latest/scripts/checkpatch/
Dcheck_known_checkpatch_issues.sh6 # SPDX-License-Identifier: Apache-2.0
12 # usage: check_known_checkpatch_issues.sh [-u]
13 # where: -u updates the known_checkpatch_issues db and commits it
14 # -q is the quiet mode (don't display the diff on stdout)
25 printf "usage: %s [-u][-q]\n" ${exe_name} >&2
30 exit -1
41 exit -1
47 declare -r optstr="quh"
62 timestamp="${timestamp_bin} -u"
64 uid=$(id -u)
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/Zephyr-latest/tests/crypto/tinycrypt/src/
Dctr_prng.c1 /* test_ctr_prng.c - TinyCrypt implementation of some CTR-PRNG tests */
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
31 * This module tests the CTR-PRNG routines
61 * AES-128 no df, PredictionResistance = False, EntropyInputLen = 256,
74 { /* Count 1 */
79 "1a062553ab60457ed1f1c52f5aca5a3be564a27545358c112ed92c6eae2cb7597cfcc2"
84 * AES-128 no df, PredictionResistance = False, EntropyInputLen = 256,
97 { /* Count 1 */
107 * AES-128 no df, PredictionResistance = False, EntropyInputLen = 256,
120 { /* Count 1 */
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/Zephyr-latest/soc/nxp/s32/common/
Dmc_me.c4 * SPDX-License-Identifier: Apache-2.0
17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v)) argument
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v)) argument
22 #define MC_ME_MODE_CONF_FUNC_RST_MASK BIT(1)
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v)) argument
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v)) argument
29 #define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v)) argument
33 #define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v)) argument
37 #define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v)) argument
38 #define MC_ME_MAIN_COREID_PIDX_MASK GENMASK(12, 8)
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/Zephyr-latest/subsys/net/lib/lwm2m/
Dlwm2m_util.c4 * SPDX-License-Identifier: Apache-2.0
15 #define SHIFT_LEFT(v, o, m) (((v) << (o)) & (m)) argument
16 #define SHIFT_RIGHT(v, o, m) (((v) >> (o)) & (m)) argument
26 int32_t e = -1, v, f = 0; in lwm2m_float_to_b32() local
28 int32_t val2 = (*in - (int32_t)*in) * PRECISION32; in lwm2m_float_to_b32()
32 return -EINVAL; in lwm2m_float_to_b32()
42 v = abs(val1); in lwm2m_float_to_b32()
45 while (v > 0) { in lwm2m_float_to_b32()
46 f >>= 1; in lwm2m_float_to_b32()
48 if (v & 1) { in lwm2m_float_to_b32()
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/Zephyr-latest/boards/intel/socfpga_std/cyclonev_socdk/doc/
Dindex.rst3 Intel® Cyclone® V SoC Development Kit
10 The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit,
15 :alt: Intel's Cyclone® V SoC FPGA DevKit
17 Intel®'s Cyclone® V SoC FPGA DevKit (Credit: Intel®)
25 Recommended board settings are the same as the GSRD for Cyclone® V
37 * J26: Short pins 1-2
38 * J27: Short pins 2-3
39 * J28: Short pins 1-2
40 * J29: Short pins 2-3
41 * J30: Short pins 1-2
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/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
22 #define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v)) argument
23 #define SWT_CR_FRZ_MASK BIT(1)
24 #define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v)) argument
26 #define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v)) argument
28 #define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v)) argument
30 #define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v)) argument
32 #define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v)) argument
34 #define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v)) argument
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/Zephyr-latest/subsys/logging/
Dlog_output_syst.c4 * SPDX-License-Identifier: Apache-2.0
30 static mipi_syst_u16 channel = 1;
34 static const char pattern[] = "SYS-T RAW DATA: ";
42 out_ctx->buf[out_ctx->control_block->offset] = (uint8_t)c; in out_func()
43 out_ctx->control_block->offset++; in out_func()
45 __ASSERT_NO_MSG(out_ctx->control_block->offset <= out_ctx->size); in out_func()
47 if (out_ctx->control_block->offset == out_ctx->size) { in out_func()
58 p->current |= (n << 4); in stp_write_putNibble()
59 p->byteDone = !p->byteDone; in stp_write_putNibble()
61 if (p->byteDone) { in stp_write_putNibble()
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/Zephyr-latest/soc/intel/intel_adsp/ace/
Dcomm_widget.h2 * SPDX-License-Identifier: Apache-2.0
29 * type: RO/V, rst: 00h
37 * type: RO/V, rst: 00h
41 #define DSATTR_SRCPID GENMASK(15, 8)
45 * type: RO/V, rst: 00h
53 * type: RO/V, rst: 0h
70 * type: RO/V, rst: 0000 0000h
73 * valid when DSUADDR.ADDRLEN bit is set to 1.
86 * type: RO/V, rst: 0000h
88 * MSB 16 address bits received in message. Valid only when ADDRLEN bit is set to 1.
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/Zephyr-latest/subsys/net/lib/http/
Dhttp_parser_url.c1 /* SPDX-License-Identifier: MIT */
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
38 (1 << ((unsigned int) (i) & 7))))
41 /* Set the mark FOR; non-destructive if mark is already set */
51 # define T(v) 0 argument
53 # define T(v) v argument
58 /* 0 nul 1 soh 2 stx 3 etx 4 eot 5 enq 6 ack 7 bel */
60 /* 8 bs 9 ht 10 nl 11 vt 12 np 13 cr 14 so 15 si */
68 /* 40 ( 41 ) 42 * 43 + 44 , 45 - 46 . 47 / */
69 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128,
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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c4 * SPDX-License-Identifier: Apache-2.0
20 #define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v argument
21 #define ahb_prescaler(v) fn_ahb_prescaler(v) argument
23 #define fn_ahb5_prescaler(v) LL_RCC_AHB5_DIV_ ## v argument
24 #define ahb5_prescaler(v) fn_ahb5_prescaler(v) argument
26 #define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v argument
27 #define apb1_prescaler(v) fn_apb1_prescaler(v) argument
29 #define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v argument
30 #define apb2_prescaler(v) fn_apb2_prescaler(v) argument
32 #define fn_apb7_prescaler(v) LL_RCC_APB7_DIV_ ## v argument
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/Zephyr-latest/arch/riscv/core/
Delf.c2 * @brief Architecture-specific relocations for RISC-V instruction sets.
7 * SPDX-License-Identifier: Apache-2.0
21 * RISC-V relocations commonly use pairs of U-type and I-type instructions.
22 * U-type instructions have 20-bit immediates, I-type instructions have 12-bit immediates.
23 * Immediates in RISC-V are always sign-extended.
24 * Thereby, this type of relocation can reach any address within a 2^31-1 byte range.
28 /* S-type has 12-bit signed immediate */
29 #define RISCV_MAX_JUMP_DISTANCE_S_TYPE ((1 << 11) - 1)
31 /* I-type has 12-bit signed immediate also */
32 #define RISCV_MAX_JUMP_DISTANCE_I_TYPE ((1 << 11) - 1)
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