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/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-i2s.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "worldsemi,ws2812-i2s"
12 include: [i2s-device.yaml, ws2812.yaml]
16 out-active-low:
20 nibble-one:
23 description: 4-bit value to shift out for a 1 pulse.
25 nibble-zero:
28 description: 4-bit value to shift out for a 0 pulse.
30 lrck-period:
35 extra-wait-time:
/Zephyr-latest/drivers/ethernet/
Deth_enc28j60_priv.h1 /* ENC28J60 Stand-alone Ethernet Controller with SPI
5 * SPDX-License-Identifier: Apache-2.0
23 * Nibble 3 : 0x0 ETH Register
26 * Nibble 2 : Bank number
27 * Nibble 1-0: Register address
175 * - Unicast
176 * - Multicast
177 * - Broadcast
178 * - CRC Check
180 * Used as default if hw-rx-filter property
[all …]
/Zephyr-latest/arch/xtensa/core/
Delf.c4 * SPDX-License-Identifier: Apache-2.0
20 * flags used (e.g. -fPIC), etc. Also not all relocation table entries should be
47 for (sh_ndx = 0; sh_ndx < ext->sect_cnt; sh_ndx++) { in xtensa_elf_relocate()
48 if (ext->sect_hdrs[sh_ndx].sh_addr <= *got_entry && in xtensa_elf_relocate()
50 ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) in xtensa_elf_relocate()
54 if (sh_ndx == ext->sect_cnt) { in xtensa_elf_relocate()
59 *got_entry += (uintptr_t)llext_loaded_sect_ptr(ldr, ext, sh_ndx) - in xtensa_elf_relocate()
60 ext->sect_hdrs[sh_ndx].sh_addr; in xtensa_elf_relocate()
76 int ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset + in xtensa_elf_relocate()
77 ELF_R_SYM(rel->r_info) * sizeof(elf_sym_t)); in xtensa_elf_relocate()
[all …]
/Zephyr-latest/lib/utils/
Dhex.c4 * SPDX-License-Identifier: Apache-2.0
15 *x = c - '0'; in char2hex()
17 *x = c - 'a' + 10; in char2hex()
19 *x = c - 'A' + 10; in char2hex()
21 return -EINVAL; in char2hex()
32 *c = x - 10 + (char)'a'; in hex2char()
34 return -EINVAL; in hex2char()
67 /* if hexlen is uneven, insert leading zero nibble */ in hex2bin()
/Zephyr-latest/doc/services/binary_descriptors/
Dindex.rst14 .. code-block:: c
22 .. code-block:: c
28 .. code-block:: bash
45 Each tag is a 16 bit unsigned integer, where the most significant nibble (4 bits) is the type
57 always aligned to 32 bits. If the value of the previous descriptor had a non-aligned
58 length, zero padding will be added to ensure that the current tag is aligned.
63 .. code-block::
78 3. It allows upstream-ability of descriptor generation (see Standard Descriptors)
82 .. code-block:: c
96 .. code-block:: kconfig
[all …]
/Zephyr-latest/include/zephyr/sys/
Dutil.h2 * Copyright (c) 2011-2014, Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
40 * @defgroup sys-util Utility Functions
63 /** Number of bits in a nibble. */
80 (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
83 * @brief Create a contiguous 64-bit bitmask starting at bit position @p l
87 (((~0ULL) - (1ULL << (l)) + 1) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
89 /** @brief 0 if @p cond is true-ish; causes a compile error otherwise. */
90 #define ZERO_OR_COMPILE_ERROR(cond) ((int) sizeof(char[1 - 2 * !(cond)]) - 1)
94 /* The built-in function used below for type checking in C is not
[all …]
/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S3 * SPDX-License-Identifier: Apache-2.0
10 #include <xtensa/xtensa-xer.h>
11 #include <xtensa/xdm-regs.h>
14 #include <xtensa/xtruntime-core-state.h>
42 .size __start, . - __start
57 #warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
76 * Even if the processor supports the non-PC-relative L32R option,
77 * it will always start up in PC-relative mode. We take advantage of
78 * this, and use PC-relative mode at least until we're sure the .lit4
81 .begin no-absolute-literals
[all …]
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h4 * SPDX-License-Identifier: Apache-2.0
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
106 /* SAF Pre-fetch optimization mode */
112 * SAF Opcode 32-bit register value.
113 * Each byte contain a SPI flash 8-bit opcode.
117 * op0 = SPI flash write-enable opcode
127 * op0 = SPI flash read 1-4-4 continuous mode opcode
128 * op1 = SPI flash op0 mode byte value for non-continuous mode
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
130 /* SAF Pre-fetch optimization mode */
136 * SAF Opcode 32-bit register value.
137 * Each byte contain a SPI flash 8-bit opcode.
141 * op0 = SPI flash write-enable opcode
151 * op0 = SPI flash read 1-4-4 continuous mode opcode
[all …]