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/Zephyr-Core-3.5.0/boards/arm/arty/dts/bindings/
Darm,daplink-qspi-mux.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "arm,daplink-qspi-mux"
14 IRQ line connected to the level-detect non-interrupt DAPLink shield
17 mux-gpios:
18 type: phandle-array
/Zephyr-Core-3.5.0/boards/arm/cc1352p1_launchxl/
Dboard_antenna.c4 * SPDX-License-Identifier: Apache-2.0
8 * Implements the RF driver callback to configure the on-board antenna
23 /* custom pinctrl states for the antenna mux */
56 GPIO_DT_SPEC_GET_BY_IDX_OR(ANTENNA_MUX, gpios, BOARD_ANT_GPIO_24G, {0}),
57 GPIO_DT_SPEC_GET_BY_IDX_OR(ANTENNA_MUX, gpios, BOARD_ANT_GPIO_PA, {0}),
58 GPIO_DT_SPEC_GET_BY_IDX_OR(ANTENNA_MUX, gpios, BOARD_ANT_GPIO_SUBG, {0}),
70 /* default pinctrl configuration: set all antenna mux control pins as GPIOs */ in board_antenna_init()
72 /* set all GPIOs to 0 (all RF paths disabled) */ in board_antenna_init()
80 * Custom TI RFCC26XX callback for switching the on-board antenna mux on radio setup.
88 /* Clear all antenna switch GPIOs (for all cases). */ in board_cc13xx_rf_callback()
[all …]
Dcc1352p1_launchxl.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "cc1352p1_launchxl-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 compatible = "ti,launchxl-cc1352p1";
24 mcuboot-led0 = &led1;
25 mcuboot-button0 = &btn1;
32 zephyr,shell-uart = &uart0;
34 zephyr,code-partition = &slot0_partition;
38 * The CC1352P LAUNCHXL has an on-board antenna switch (SKY13317-373LF) used to select the
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/Zephyr-Core-3.5.0/dts/bindings/i2c/
Dti,tca954x-base.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for TI TCA954X I2C mux family
14 mux: tca9546a@77 {
18 #address-cells = <1>;
19 #size-cells = <0>;
20 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
23 compatible: "ti,tca9546a-channel"
25 #address-cells = <1>;
26 #size-cells = <0>;
35 compatible: "ti,tca9546a-channel"
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/Zephyr-Core-3.5.0/boards/arm/cc1352p1_launchxl/dts/bindings/
Dskyworks,sky13317.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [pinctrl-device.yaml, base.yaml]
11 gpios:
12 type: phandle-array
14 description: Antenna mux control pins
/Zephyr-Core-3.5.0/dts/bindings/dac/
Despressif,esp32-dac.yaml2 # SPDX-License-Identifier: Apache-2.0
6 is part of the RTC low-power domain and belongs to the SENSE
7 peripherals set. RTC peripherals has GPIOs controlled by the
8 RTCIO mux, which is separated from the main IO mux.
13 - GPIO25 as DAC channel 1
14 - GPIO26 as DAC channel 2
16 ESP32-S2 pads
17 - GPIO17 as DAC channel 1
18 - GPIO18 as DAC channel 2
28 properties 'dac-channel-id', which uses zero based channel index.
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/Zephyr-Core-3.5.0/boards/arm/arty/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
39 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
43 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
48 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dgpio-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
7 "gpio-controller":
11 "#gpio-cells":
19 This property indicates the number of in-use slots of available slots
20 for GPIOs. The typical example is something like this: the hardware
25 "ngpios = <18>;" informs the driver that only the first 18 GPIOs, at
28 gpio-reserved-ranges:
31 If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
32 this property contains an additional set of tuples which specify which GPIOs
33 are unusable. This property indicates the start and size of the GPIOs
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/Zephyr-Core-3.5.0/dts/bindings/net/wireless/
Dnordic,nrf21540-fem.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This is a representation of the nRF21540 Radio Front-End module.
8 See the "nordic,nrf21540-fem-spi" binding to configure the SPI
11 the FEM and SPI configurations using the spi-if property.
17 compatible = "nordic,nrf-spim";
19 cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
22 my_spi_if: nrf21540-spi@0 {
23 compatible = "nordic,nrf21540-fem-spi";
25 spi-max-frequency = <8000000>;
30 compatible = "nordic,nrf21540-fem";
[all …]
/Zephyr-Core-3.5.0/tests/lib/devicetree/api/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 test-alias = &test_nodelabel;
28 #address-cells = < 0x1 >;
29 #size-cells = < 0x1 >;
30 interrupt-parent = <&test_intc>;
32 test_pinctrl: pin-controller {
34 test_pincfg_a: pincfg-a {};
35 test_pincfg_b: pincfg-b {};
36 test_pincfg_c: pincfg-c {};
[all …]
/Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
30 out_dev->name, in_dev->name); in board_setup()
37 * Configure pin mux. in board_setup()
38 * The following code needs to configure the same GPIOs which were in board_setup()
97 /* This functions allows to programmatically short-circuit SOC GPIO pins */ in board_setup()
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_rt1015.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 clock-frequency = <500000000>;
27 ipg-podf {
28 clock-div = <4>;
37 /delete-node/ &lpspi3;
38 /delete-node/ &lpspi4;
43 /delete-node/ adc@400C8000;
44 /* GPIOS 4 and 6-9 are not preset on RT1015 */
45 /delete-node/ gpio@401c4000;
46 /delete-node/ gpio@42000000;
[all …]
Dnxp_rt1020.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 clock-frequency = <500000000>;
27 ipg-podf {
28 clock-div = <4>;
38 /* GPIOS 4 and 6-9 are not preset on RT1020 */
39 /delete-node/ gpio@401c4000;
40 /delete-node/ gpio@42000000;
41 /delete-node/ gpio@42004000;
42 /delete-node/ gpio@42008000;
43 /delete-node/ gpio@4200c000;
[all …]
Dnxp_rt1050.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 arm-podf {
10 clock-div = <2>;
13 ipg-podf {
14 clock-div = <4>;
20 /* GPIOS 6-9 are not preset on RT1050 */
21 /delete-node/ gpio@42000000;
22 /delete-node/ gpio@42004000;
23 /delete-node/ gpio@42008000;
24 /delete-node/ gpio@4200c000;
[all …]
Dnxp_rt1024.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 clock-frequency = <500000000>;
32 ipg-podf {
33 clock-div = <4>;
42 compatible = "nxp,imx-flexspi-nor";
45 spi-max-frequency = <133000000>;
47 jedec-id = [9d 70 17];
48 erase-block-size = <DT_SIZE_K(4)>;
49 write-block-size = <1>;
55 /* GPIOS 4 and 6-9 are not preset on RT1024 */
[all …]
Dnxp_kw2xd.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
4 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/adc.h>
6 #include <zephyr/dt-bindings/clock/kinetis_sim.h>
7 #include <zephyr/dt-bindings/clock/kinetis_mcg.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <nxp/kinetis/MKW24D512VHA5-pinctrl.h>
21 zephyr,flash-controller = &ftfl;
25 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/boards/arm/stm32g081b_eval/doc/
Dindex.rst8 The STM32G081B-EVAL Evaluation board is a high-end development platform, for
9 Arm Cortex-M0+ core-based STM32G081RBT6 microcontroller, with USB Type-C and
10 power delivery controller interfaces (UCPD), compliant with USB type-C r1.2
12 one 12-bit ADC, two 12-bit DACs, two GP comparators, two LP timers, internal
14 hardware features on the STM32G081B-EVAL Evaluation board includes a mother
15 board, a legacy peripheral daughterboard and a USB-C and Power Delivery
16 daughterboard, which help to evaluate all peripherals (USB Type-C connector
22 The board integrates an ST-LINK/V2-1 as an embedded in-circuit debugger and
27 The USB-C and Power Delivery daughterboard
28 features two independent USB-C ports controlled by an STM32G0. USB-C port 1
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/Zephyr-Core-3.5.0/boards/xtensa/esp32_ethernet_kit/doc/
Dindex.rst3 ESP32-ETHERNET-KIT
6 The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables
7 Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide
8 more flexible power supply options, the ESP32-Ethernet-Kit also supports power
11 .. _get-started-esp32-ethernet-kit-v1.2-overview:
13 .. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg
15 :alt: ESP32-Ethernet-Kit V1.2
16 :figclass: align-center
18 ESP32-Ethernet-Kit V1.2 Overview
23 ESP32-Ethernet-Kit is an ESP32-based development board produced by
[all …]
/Zephyr-Core-3.5.0/tests/lib/devicetree/api/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
9 * - DT_LABEL
10 * - DT_BUS_LABEL
11 * - DT_SPI_DEV_CS_GPIOS_LABEL
12 * - DT_GPIO_LABEL
13 * - DT_GPIO_LABEL_BY_IDX
14 * - DT_INST_LABEL
15 * - DT_INST_BUS_LABEL
16 * - DT_INST_SPI_DEV_CS_GPIOS_LABEL
17 * - DT_INST_GPIO_LABEL
[all …]
/Zephyr-Core-3.5.0/boards/arc/hsdk4xd/doc/
Dindex.rst10 It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces
19 (HSDK4xD) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
24 The ARC HSDK4xD has 24 general GPIOs, which divided into 8 groups named from ``GPIO_SEL_0`` to ``GP…
29 +--------+-------------+---------+--------------+---------------------------------+
31 +--------+-------------+---------+--------------+---------------------------------+
32 | 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] |
33 +--------+-------------+---------+--------------+---------------------------------+
34 | 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] |
35 +--------+-------------+---------+--------------+---------------------------------+
36 | 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] |
[all …]
/Zephyr-Core-3.5.0/boards/arc/hsdk/doc/
Dindex.rst9 The DesignWare(R) ARC(R) HS Development Kit is a ready-to-use platform for
11 single-core and multi-core ARC HS34, HS36 and HS38 processors and offers a wide
22 (HSDK) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
27 The ARC HSDK has 24 general GPIOs, which divided into 8 groups named from GPIO_SEL_0 to GPIO_SEL_7.
32 +--------+-------------+---------+--------------+---------------------------------+
34 +--------+-------------+---------+--------------+---------------------------------+
35 | 2:0 | GPIO_SEL_0 | RW | 0x0* | GPIO mux select for gpio[3:0] |
36 +--------+-------------+---------+--------------+---------------------------------+
37 | 5:3 | GPIO_SEL_1 | RW | 0x0* | GPIO mux select for gpio[7:4] |
38 +--------+-------------+---------+--------------+---------------------------------+
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_nct38xx_port.c4 * SPDX-License-Identifier: Apache-2.0
43 const struct gpio_nct38xx_port_config *const config = dev->config; in gpio_nct38xx_pin_config()
44 struct gpio_nct38xx_port_data *const data = dev->data; in gpio_nct38xx_pin_config()
51 return -ENOTSUP; in gpio_nct38xx_pin_config()
56 return -ENOTSUP; in gpio_nct38xx_pin_config()
59 /* Don't support pull-up/pull-down */ in gpio_nct38xx_pin_config()
61 return -ENOTSUP; in gpio_nct38xx_pin_config()
64 k_sem_take(data->lock, K_FOREVER); in gpio_nct38xx_pin_config()
67 if (config->gpio_port == 0) { in gpio_nct38xx_pin_config()
68 /* Set the mux control bit, but ensure the reserved fields in gpio_nct38xx_pin_config()
[all …]
/Zephyr-Core-3.5.0/doc/build/dts/api/
Dapi.rst10 Some of these -- the ones beginning with ``DT_INST_`` -- require a special
19 .. _devicetree-generic-apis:
33 :ref:`devicetree-property-access` API.
45 .. doxygengroup:: devicetree-generic-id
47 .. _devicetree-property-access:
52 The following general-purpose macros can be used to access node properties.
53 There are special-purpose APIs for accessing the :ref:`devicetree-ranges-property`,
54 :ref:`devicetree-reg-property` and :ref:`devicetree-interrupts-property`.
59 .. doxygengroup:: devicetree-generic-prop
61 .. _devicetree-ranges-property:
[all …]
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
[all …]
/Zephyr-Core-3.5.0/drivers/espi/
Despi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/espi/npcx_espi.h>
31 /* mapping table between eSPI reset signal and wake-up input */
52 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
106 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
110 uint8_t bitmask; /* VW signal bits-mask */
114 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
118 uint8_t bitmask; /* VW signal bits-mask */
123 * npcxn-espi-vws-map.dtsi device tree file for more detail.
164 /* Virtual wire GPIOs for platform level usage (High at Reset state) */
[all …]

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