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/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 MSI Clock
6 compatible: "st,stm32-msi-clock"
8 include: [clock-controller.yaml, base.yaml]
11 msi-range:
16 MSI clock ranges
18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
[all …]
Dst,stm32u5-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32u5-msi-clock"
9 - name: st,stm32-msi-clock.yaml
10 property-blocklist:
11 - msi-range
15 msi-range:
20 MSI clock ranges
22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
[all …]
Dst,stm32l0-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32l0-msi-clock"
9 - name: st,stm32-msi-clock.yaml
10 property-blocklist:
11 - msi-range
14 msi-range:
19 MSI clock ranges
21 - 0 # range 0, around 65.536 kHz
22 - 1 # range 1, around 131.072 kHz
23 - 2 # range 2, around 262.144 kHz
[all …]
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
Dspi1_msik.overlay4 * SPDX-License-Identifier: Apache-2.0
13 msi-range = <4>;
14 msi-pll-mode;
19 /delete-property/ clocks;
/Zephyr-Core-3.6.0/drivers/disk/nvme/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
11 driver to support these. It will enable MSI-X and MSI multi-vector
18 range 2 4096
26 range 1 65536
34 range 2 65536
44 This sets the amount of possible retries per-request.
49 range 5 120
59 This sets the amount of pre-allocated PRP list. Each list
66 range 1 16
77 Interrupt priority used for the MSI-X generated interrupts.
[all …]
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dclear_msi.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * Warning: This overlay clears the msi clock back to a state equivalent to what could
14 /delete-property/ msi-range;
Dwb_pll_48_msi_4.overlay4 * SPDX-License-Identifier: Apache-2.0
10 * It applies to the stm32wb where the msi is 4MHz
15 msi-range = <6>; /* default value */
19 div-m = <1>;
20 mul-n = <24>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(48)>;
Dpll_48_msi_4.overlay4 * SPDX-License-Identifier: Apache-2.0
10 * It applies to the stm32xx where the msi is 4MHz
15 msi-range = <6>; /* default value */
19 div-m = <1>;
20 mul-n = <24>;
21 div-q = <2>;
22 div-r = <2>;
29 clock-frequency = <DT_FREQ_M(48)>;
Dmsi_range6.overlay4 * SPDX-License-Identifier: Apache-2.0
14 msi-range = <6>;
19 clock-frequency = <4194304>;
Dmsi_range11.overlay4 * SPDX-License-Identifier: Apache-2.0
14 msi-range = <11>;
19 clock-frequency = <DT_FREQ_M(48)>;
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dmsis_24.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <1>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(24)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dmsis_48.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <0>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(48)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dpll_msis_160.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <2>;
26 div-r = <2>;
33 clock-frequency = <DT_FREQ_M(160)>;
34 ahb-prescaler = <1>;
35 apb1-prescaler = <1>;
[all …]
Dpll_msis_ahb_2_40.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <4>;
26 div-r = <4>;
33 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
34 clock-frequency = <DT_FREQ_M(40)>;
35 apb1-prescaler = <1>;
[all …]
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-bypass;
28 /delete-property/ msi-range;
29 /delete-property/ msi-pll-mode;
33 /delete-property/ div-m;
34 /delete-property/ mul-n;
35 /delete-property/ div-q;
36 /delete-property/ div-r;
37 /delete-property/ clocks;
[all …]
/Zephyr-Core-3.6.0/drivers/virtualization/
DKconfig3 # Copyright (c) 2015-2020 Intel Corporation
4 # SPDX-License-Identifier: Apache-2.0
16 bool "Inter-VM shared memory device (ivshmem)"
26 module-str = ivshmem
32 This will enable support of ivshmem-doorbell, i.e. the interrupt
33 based ivshmem. For ivshmem-v2 INTx interrupts are also supported.
36 int "How many notification vectors should be pre-allocated?"
40 MSI-X vector holders must be pre-allocated. One can pre-allocate
46 int "MSI-X interrupt priority"
50 Interrupt priority used for the MSI-X generated interrupts.
[all …]
/Zephyr-Core-3.6.0/drivers/clock_control/
DKconfig.stm325 # SPDX-License-Identifier: Apache-2.0
14 $(dt_nodelabel_has_prop,clk_hse,css-enabled))
22 DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency)
29 Value of external high-speed clock (HSE). This symbol could be optionally
30 configured using device tree by setting "clock-frequency" value of clk_hse
34 clock-frequency = <DT_FREQ_M(25)>;
49 # Micro-controller Clock output configuration options
94 bool "MSI"
97 Use MSI as source of MCO1
177 range 1 5 if SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
[all …]
/Zephyr-Core-3.6.0/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-Core-3.6.0/soc/arm/st_stm32/stm32l1/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/linker/linker-defs.h>
32 /* At reset, system core clock is set to 2.1 MHz from MSI */ in stm32l1_init()
35 /* Default Voltage scaling range selection (range2) in stm32l1_init()
/Zephyr-Core-3.6.0/include/zephyr/drivers/pcie/endpoint/
Dpcie_ep.h8 * SPDX-License-Identifier: Apache-2.0
22 PCIE_OB_ANYMEM, /**< PCIe OB window within any address range */
23 PCIE_OB_LOWMEM, /**< PCIe OB window within 32-bit address range */
24 PCIE_OB_HIGHMEM, /**< PCIe OB window above 32-bit address range */
29 PCIE_EP_IRQ_MSI, /**< Raise MSI interrupt */
50 * interrupt-safe APIS. Registration of callbacks is done via
95 (const struct pcie_ep_driver_api *)dev->api; in pcie_ep_conf_read()
97 return api->conf_read(dev, offset, data); in pcie_ep_conf_read()
114 (const struct pcie_ep_driver_api *)dev->api; in pcie_ep_conf_write()
116 api->conf_write(dev, offset, data); in pcie_ep_conf_write()
[all …]
/Zephyr-Core-3.6.0/soc/arm/st_stm32/stm32l0/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/linker/linker-defs.h>
33 /* At reset, system core clock is set to 2.1 MHz from MSI */ in stm32l0_init()
36 /* Default Voltage scaling range selection (range2) in stm32l0_init()
45 * See https://github.com/zephyrproject-rtos/zephyr/issues/#37119 in stm32l0_init()
48 * https://github.com/zephyrproject-rtos/zephyr/issues/#34324 ) in stm32l0_init()
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]

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