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Searched +full:msi +full:- +full:pll +full:- +full:mode (Results 1 – 22 of 22) sorted by relevance

/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 MSI Clock
6 compatible: "st,stm32-msi-clock"
8 include: [clock-controller.yaml, base.yaml]
11 msi-range:
16 MSI clock ranges
18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
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/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
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Dspi1_msik.overlay4 * SPDX-License-Identifier: Apache-2.0
13 msi-range = <4>;
14 msi-pll-mode;
19 /delete-property/ clocks;
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dmsis_24.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <1>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(24)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dmsis_48.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <0>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(48)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dpll_msis_160.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <2>;
26 div-r = <2>;
33 clock-frequency = <DT_FREQ_M(160)>;
34 ahb-prescaler = <1>;
35 apb1-prescaler = <1>;
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Dpll_msis_ahb_2_40.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <4>;
26 div-r = <4>;
33 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
34 clock-frequency = <DT_FREQ_M(40)>;
35 apb1-prescaler = <1>;
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Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-bypass;
28 /delete-property/ msi-range;
29 /delete-property/ msi-pll-mode;
33 /delete-property/ div-m;
34 /delete-property/ mul-n;
35 /delete-property/ div-q;
36 /delete-property/ div-r;
37 /delete-property/ clocks;
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/Zephyr-Core-3.6.0/boards/arm/stm32l4r9i_disco/
Dstm32l4r9i_disco.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
8 #include <st/l4/stm32l4r9a(g-i)ix-pinctrl.dtsi>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics STM32L4R9I-DISCO board";
14 compatible = "st,stm32l4r9i-disco";
18 zephyr,shell-uart = &usart2;
24 compatible = "gpio-leds";
33 compatible = "gpio-keys";
44 die-temp0 = &die_temp;
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/Zephyr-Core-3.6.0/boards/arm/stm32l562e_dk/
Dstm32l562e_dk_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/l5/stm32l562qeixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "gpio-leds";
26 compatible = "gpio-keys";
35 spi-flash0 = &mx25lm51245;
36 die-temp0 = &die_temp;
37 volt-sensor0 = &vref;
38 volt-sensor1 = &vbat;
48 msi-range = <6>;
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/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_u5.c6 * SPDX-License-Identifier: Apache-2.0
52 /** @brief returns the pll source frequency of given pll_id */
70 __ASSERT(0, "No PLL Source configured"); in get_pllsrc_frequency()
145 return -ENOTSUP; in enabled_clock()
155 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
157 return -ENOTSUP; in stm32_clock_control_on()
160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
161 pclken->enr); in stm32_clock_control_on()
173 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
175 return -ENOTSUP; in stm32_clock_control_off()
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Dclock_stm32_ll_common.c2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
50 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
55 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
61 * @brief Return frequency for pll with 2 dividers and a multiplier
111 r = -ENOTSUP; in enabled_clock()
118 r = -ENOTSUP; in enabled_clock()
125 r = -ENOTSUP; in enabled_clock()
132 r = -ENOTSUP; in enabled_clock()
139 r = -ENOTSUP; in enabled_clock()
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/Zephyr-Core-3.6.0/boards/arm/nucleo_u575zi_q/
Dnucleo_u575zi_q-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/u5/stm32u575zitxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "gpio-leds";
30 compatible = "gpio-keys";
39 compatible = "pwm-leds";
64 msi-range = <4>;
65 msi-pll-mode;
69 div-m = <1>;
70 mul-n = <80>;
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/Zephyr-Core-3.6.0/boards/arm/nucleo_u5a5zj_q/
Dnucleo_u5a5zj_q-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/u5/stm32u5a5zjtxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "gpio-leds";
30 compatible = "gpio-keys";
39 compatible = "pwm-leds";
64 msi-range = <4>;
65 msi-pll-mode;
69 div-m = <1>;
70 mul-n = <80>;
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/Zephyr-Core-3.6.0/boards/arm/b_u585i_iot02a/
Db_u585i_iot02a-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "gpio-leds";
26 compatible = "gpio-keys";
37 spi-flash0 = &mx25lm51245;
38 die-temp0 = &die_temp;
39 volt-sensor0 = &vref1;
40 volt-sensor1 = &vbat4;
54 msi-range = <4>;
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/Zephyr-Core-3.6.0/boards/arm/disco_l475_iot1/
Ddisco_l475_iot1.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/l4/stm32l475v(c-e-g)tx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics B-L475E-IOT01Ax board";
15 compatible = "st,stm32l475-disco-iot";
19 zephyr,shell-uart = &usart1;
22 zephyr,code-partition = &slot0_partition;
23 zephyr,flash-controller = &mx25r6435f;
27 compatible = "gpio-leds";
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/Zephyr-Core-3.6.0/boards/arm/sensortile_box_pro/
Dsensortile_box_pro.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics SENSORTILE-BOX-PRO board";
14 compatible = "st,sensortile-box-pro";
24 * zephyr,shell-uart = &uart4;
27 zephyr,shell-uart = &cdc_acm_uart0;
31 zephyr,code-partition = &slot0_partition;
35 compatible = "gpio-leds";
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/Zephyr-Core-3.6.0/boards/arm/stm32u5a9j_dk/
Dstm32u5a9j_dk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u5a9njhxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32u5a9j-dk";
18 zephyr,shell-uart = &usart1;
21 zephyr,code-partition = &slot0_partition;
25 compatible = "gpio-leds";
37 compatible = "gpio-keys";
46 compatible = "st,dsi-lcd-qsh-030";
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/Zephyr-Core-3.6.0/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
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Drelease-notes-3.1.rst32 * Disk Subsystem: SPI mode SD cards now use the SD subsystem to communicate
61 * Split CAN classic and CAN-FD APIs:
68 * Converted the ``enum can_mode`` into a ``can_mode_t`` bitfield and renamed the CAN mode
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
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Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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