Searched full:misc (Results 1 – 25 of 27) sorted by relevance
12
65 P_CC3XX->misc.hash_clk_enable = 0x1U; in init_without_iv_set()142 P_CC3XX->misc.hash_clk_enable = 0x0U; in cc3xx_lowlevel_hash_uninit()
84 P_CC3XX->misc.dma_clk_enable = 0x1U; in process_data()139 P_CC3XX->misc.dma_clk_enable = 0x0U; in process_data()
84 P_CC3XX->misc.chacha_clk_enable = 0x1U; in chacha_init_from_state()404 P_CC3XX->misc.chacha_clk_enable = 0; in cc3xx_lowlevel_chacha20_uninit()
288 /* Misc Block */308 } misc;
344 P_CC3XX->misc.aes_clk_enable = 0x1U; in init_from_state()426 P_CC3XX->misc.hash_clk_enable = 0x1; in init_from_state()1140 P_CC3XX->misc.aes_clk_enable = 0x0U; in cc3xx_lowlevel_aes_uninit()
167 P_CC3XX->misc.pka_clk_enable = 1; in pka_init_from_state()543 P_CC3XX->misc.pka_clk_enable = 0; in cc3xx_lowlevel_pka_uninit()
54 volatile uint32_t MISC; /* Offset: 0x04C (R/W) Misc control member
16 misc:
15 misc:
6 misc:
20 rsource "Kconfig.misc"
73 ################################# Misc #########################################
182 // BLOCK: MISC
1123 <td>block: <a href="#1.6">MISC</a></td>2119 …a><br><a href="#1.4">AES</a><br><a href="#1.5">HASH</a><br><a href="#1.6">MISC</a><br><a href="#1.…8086 <td><b><font color="#000000">1.6 : Block: MISC</font></b></td>
1401 … 4U /*!< MVFR2: VFP Misc bits Position */1402 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1620 … 4U /*!< MVFR2: VFP Misc bits Position */1621 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1770 … 4U /*!< MVFR2: VFP Misc bits Position */1771 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1864 … 4U /*!< MVFR2: VFP Misc bits Position */1865 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
3278 … 4U /*!< MVFR2: VFP Misc bits Position */3279 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
3228 … 4U /*!< MVFR2: VFP Misc bits Position */3229 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
3252 … 4U /*!< MVFR2: VFP Misc bits Position */3253 …_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
