| /Zephyr-Core-3.5.0/arch/arm/core/mpu/ |
| D | arm_core_mpu_dev.h | 4 * SPDX-License-Identifier: Apache-2.0
22 * @brief Maximum number of memory domain partitions
24 * This internal macro returns the maximum number of memory partitions, which
25 * may be defined in a memory domain, given the amount of available HW MPU
28 * @param mpu_regions_num the number of available HW MPU regions.
33 * For ARM MPU architectures, where the domain partitions cannot be defined
34 * on top of the statically configured memory regions, the maximum number of
35 * memory domain partitions is set to half of the number of available MPU
36 * regions. This ensures that in the worst-case where there are gaps between
37 * the memory partitions of the domain, the desired memory map can still be
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| D | Kconfig | 1 # Memory Protection Unit (MPU) configuration options
4 # SPDX-License-Identifier: Apache-2.0
9 bool "ARM MPU Support"
10 select MPU
18 MCU implements Memory Protection Unit.
21 The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
22 alignment of MPU region base address and size.
24 The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
25 to have power-of-two alignment for base address and region size.
27 The ARMv8-M MPU requires the active MPU regions be non-overlapping.
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| D | nxp_mpu.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/linker/linker-defs.h>
17 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
21 LOG_MODULE_DECLARE(mpu);
28 "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
31 * Global status variable holding the number of HW MPU region indices, which
32 * have been reserved by the MPU driver to program the static (fixed) memory
37 /* Global MPU configuration at system initialization. */
40 /* Enable clock for the Memory Protection Unit (MPU). */ in mpu_init()
45 * Get the number of supported MPU regions.
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| D | arm_mpu.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
19 LOG_MODULE_DECLARE(mpu);
22 /* The order here is on purpose since ARMv8-M SoCs may define
24 * so we want to check for ARMv8-M first.
42 "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
45 * Global status variable holding the number of HW MPU region indices, which
46 * have been reserved by the MPU driver to program the static (fixed) memory
51 /* Include architecture-specific internal headers. */
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| D | arm_mpu_v8_internal.h | 5 * SPDX-License-Identifier: Apache-2.0
19 * memory areas where dynamic MPU programming
28 * Global array, holding the MPU region index of
29 * the memory region inside which dynamic memory
37 MPU->MAIR0 = mair0; in mpu_set_mair0()
42 MPU->RNR = rnr; in mpu_set_rnr()
47 MPU->RBAR = rbar; in mpu_set_rbar()
52 return MPU->RBAR; in mpu_get_rbar()
57 MPU->RLAR = rlar; in mpu_set_rlar()
62 return MPU->RLAR; in mpu_get_rlar()
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| D | arm_mpu_v7_internal.h | 5 * SPDX-License-Identifier: Apache-2.0
18 /* Global MPU configuration at system initialization. */
21 /* No specific configuration at init for ARMv7-M MPU. */ in mpu_init()
24 /* This internal function performs MPU region initialization.
27 * The caller must provide a valid region index.
32 /* Select the region you want to access */ in region_init()
35 /* Configure the region */ in region_init()
43 set_region_base_address(region_conf->base & MPU_RBAR_ADDR_Msk); in region_init()
44 set_region_attributes(region_conf->attr.rasr); in region_init()
45 set_region_size(region_conf->size | MPU_RASR_ENABLE_Msk); in region_init()
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| D | arm_core_mpu.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
17 LOG_MODULE_REGISTER(mpu);
23 * Maximum number of dynamic memory partitions that may be supplied to the MPU
24 * driver for programming during run-time. Note that the actual number of the
25 * available MPU regions for dynamic programming depends on the number of the
26 * static MPU regions currently being programmed, and the total number of HW-
27 * available MPU regions. This macro is only used internally in function
41 * memory area, where dynamic memory regions may be programmed at run-time.
48 #define _MPU_DYNAMIC_REGIONS_AREA_SIZE ((uint32_t)&__kernel_ram_end - \
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| /Zephyr-Core-3.5.0/arch/arc/core/mpu/ |
| D | arc_mpu_common_internal.h | 4 * SPDX-License-Identifier: Apache-2.0
14 #error "Unsupported MPU version"
18 * @brief configure the base address and size for an MPU region
20 * @param type MPU region type
22 * @param size size of the region
29 LOG_DBG("Region info: 0x%x 0x%x", base, size); in _mpu_configure()
32 return -EINVAL; in _mpu_configure()
36 * For ARC MPU, MPU regions can be overlapped, smaller in _mpu_configure()
37 * region index has higher priority. in _mpu_configure()
44 /* ARC Core MPU Driver API Implementation for ARC MP */
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| D | arc_mpu_v4_internal.h | 4 * SPDX-License-Identifier: Apache-2.0
15 /* For MPU version 4, the minimum protection region size is 32 bytes */
19 (start + size - (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS))
21 /* ARC MPU version 4 does not support mpu region overlap in hardware
22 * so if we want to allocate MPU region dynamically, e.g. thread stack,
23 * memory domain from a background region, a dynamic region splitting
27 * As a trade off, we can use the default mpu region as the background region
28 * to avoid the dynamic region splitting. This will give more privilege to
29 * codes in kernel mode which can access the memory region not covered by
30 * explicit mpu entry. Considering memory protection is mainly used to
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| D | Kconfig | 1 # Memory Protection Unit (MPU) configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 int "ARC MPU version"
11 ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes;
12 For other versions, the minimum region is 32 bytes; v4 has secure features,
13 v6 supports up to 32 regions. Note: MPU v5 & v7 are not supported.
16 bool "ARC Core MPU functionalities"
18 ARC core MPU functionalities
24 Enable thread stack guards via MPU. ARC supports built-in stack protection.
25 If your core supports that, it is preferred over MPU stack guard.
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| /Zephyr-Core-3.5.0/arch/arm/include/cortex_m/ |
| D | cmse.h | 4 * SPDX-License-Identifier: Apache-2.0
11 * CMSE API for Cortex-M23/M33 CPUs.
34 * security states and privilege levels have on memory at a specified address
38 * @brief Get the MPU region number of an address
40 * Return the non-negative MPU region that the address maps to,
41 * or -EINVAL to indicate that an invalid MPU region was retrieved.
44 * Obtained region is valid only if:
45 * - the function is called from privileged mode
46 * - the MPU is implemented and enabled
47 * - the given address matches a single, enabled MPU region
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| /Zephyr-Core-3.5.0/doc/services/mem_mgmt/ |
| D | index.rst | 3 Memory Attributes
6 It is possible in the devicetree to mark the memory regions with attributes by
7 using the ``zephyr,memory-attr`` property. This property and the related memory
8 region can then be retrieved at run-time by leveraging a provided helper
12 and explained in :zephyr_file:`include/zephyr/dt-bindings/memory-attr/memory-attr.h`.
14 For example, to mark a memory region in the devicetree as non-volatile, cacheable,
15 out-of-order:
17 .. code-block:: devicetree
19 mem: memory@10000000 {
20 compatible = "mmio-sram";
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| /Zephyr-Core-3.5.0/boards/arm/arty/ |
| D | arty_a7_arm_designstart_m3.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <arm/armv7-m.dtsi>
12 model = "Digilent Arty A7 ARM DesignStart Cortex-M3";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m3";
22 #address-cells = <1>;
23 #size-cells = <1>;
25 mpu: mpu@e000ed90 { label
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| /Zephyr-Core-3.5.0/tests/kernel/mem_heap/shared_multi_heap/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/linker/linker-defs.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
22 struct shared_multi_heap_region region; member
28 .region = { \
41 static void smh_reg_map(struct shared_multi_heap_region *region) in smh_reg_map() argument
46 mem_attr = (region->attr == SMH_REG_ATTR_CACHEABLE) ? K_MEM_CACHE_WB : K_MEM_CACHE_NONE; in smh_reg_map()
49 z_phys_map(&v_addr, region->addr, region->size, mem_attr); in smh_reg_map()
51 region->addr = (uintptr_t) v_addr; in smh_reg_map()
56 * Given a virtual address retrieve the original memory region that the mapping
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| /Zephyr-Core-3.5.0/arch/arm64/core/cortex_r/ |
| D | Kconfig | 1 # Memory Protection Unit (MPU) configuration options
6 # SPDX-License-Identifier: Apache-2.0
11 bool "ARM MPU Support"
13 select MPU
18 MPU implements Memory Protection Unit.
21 The ARMv8-R MPU architecture requires a power-of-two alignment
22 of MPU region base address and size(64 bytes aligned).
24 The ARMv8-R MPU requires the active MPU regions be non-overlapping.
25 As a result of this, the ARMv8-R MPU needs to fully partition the
26 memory map when programming dynamic memory regions (e.g. PRIV stack
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| D | arm_mpu.c | 5 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
20 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
22 LOG_MODULE_REGISTER(mpu, CONFIG_MPU_LOG_LEVEL);
29 "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
49 #define MPU_DYNAMIC_REGIONS_AREA_SIZE ((size_t)((uintptr_t)&__kernel_ram_end - \
54 * AArch64 Memory Model Feature Register 0
55 * Provides information about the implemented memory model and memory
58 * Armv8, for Armv8-R AArch64 architecture profile, G1.3.7
68 * Global status variable holding the number of HW MPU region indices, which
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| /Zephyr-Core-3.5.0/dts/bindings/base/ |
| D | zephyr,memory-attr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 zephyr,memory-region-mpu:
11 Signify that this node should result in a dedicated MPU region.
12 Deprecated in favor of 'zephyr,memory-attr'.
14 zephyr,memory-attr:
17 Attribute or set of attributes (bitmask) for the memory region. See
18 'include/zephyr/dt-bindings/memory-attr/memory-attr.h' for a
|
| /Zephyr-Core-3.5.0/boards/arm/mps2_an521/ |
| D | mps2_an521_remote.dts | 2 * Copyright (c) 2018-2019 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <arm/armv8-m.dtsi>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
29 zephyr,shell-uart = &uart0;
35 compatible = "gpio-leds";
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| D | mps2_an521_ns.dts | 2 * Copyright (c) 2018-2019 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <arm/armv8-m.dtsi>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
29 zephyr,shell-uart = &uart0;
35 compatible = "gpio-leds";
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| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/mimx8ml8_m7/ |
| D | mpu_regions.c | 4 * SPDX-License-Identifier: Apache-2.0
23 * Region 0 [0x0000_0000 - 0x4000_0000]:
24 * Memory with Device type, not executable, not shareable, non-cacheable.
31 * Region 1 ITCM[0x0000_0000 - 0x0001_FFFF]:
32 * Memory with Normal type, not shareable, non-cacheable
39 * Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]:
40 * Memory with Normal type, not shareable, cacheable
47 * Region 3 DTCM[0x2000_0000 - 0x2002_0000]:
48 * Memory with Normal type, not shareable, non-cacheable
55 * Region 4 DDR[0x4000_0000 - 0x8000_0000]:
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| /Zephyr-Core-3.5.0/soc/arm/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
10 This option is enabled when the CPU has a Memory Protection Unit (MPU)
17 This option is enabled when the CPU has a Memory Protection Unit (MPU)
21 bool "Custom fixed SoC MPU region definition"
24 define and configure its own fixed MPU regions in the
25 SoC definition. These fixed MPU regions are currently
40 MCU implements the nRF (vendor-specific) Security Attribution Unit.
41 (IDAU: "Implementation-Defined Attribution Unit", in accordance with
50 FLASH region size for the NRF_SPU peripheral
56 RAM region size for the NRF_SPU peripheral
|
| /Zephyr-Core-3.5.0/doc/kernel/usermode/ |
| D | memory_domain.rst | 3 Memory Protection Design
6 Zephyr's memory protection design is geared towards microcontrollers with MPU
7 (Memory Protection Unit) hardware. We do support some architectures, such as x86,
8 which have a paged MMU (Memory Management Unit), but in that case the MMU is
9 used like an MPU with an identity page table.
11 All of the discussion below will be using MPU terminology; systems with MMUs
12 can be considered to have an MPU with an unlimited number of programmable
15 There are a few different levels on how memory access is configured when
16 Zephyr memory protection features are enabled, which we will describe here:
18 Boot Time Memory Configuration
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| /Zephyr-Core-3.5.0/samples/subsys/ipc/openamp/boards/ |
| D | mimxrt1170_evkb_cm7.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory.
15 * Define a subset of the OCRAM2 region for demo to use
16 * Note that shared memory must have specific MPU attributes set.
18 ocram2_overlay: memory@202c0000{
19 compatible = "zephyr,memory-region", "mmio-sram";
21 zephyr,memory-region="OCRAM2_OVERLAY";
22 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
|
| D | mimxrt1160_evk_cm7.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory.
15 * Define a subset of the OCRAM2 region for demo to use
16 * Note that shared memory must have specific MPU attributes set.
18 ocram2_overlay: memory@202c0000{
19 compatible = "zephyr,memory-region", "mmio-sram";
21 zephyr,memory-region="OCRAM2_OVERLAY";
22 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
|
| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/k6x/ |
| D | nxp_mpu_regions.c | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/arch/arm/mpu/nxp_mpu.h>
10 /* Region 0 */
12 * to access RAM when their regions are dynamically disabled in NXP MPU.
19 /* The NXP MPU does not give precedence to memory regions like the ARM
20 * MPU, which means that if one region grants access then another
21 * region cannot revoke access. If an application enables hardware
23 * to the stack guard region. As a result, we cannot have a single
24 * background region that enables supervisor read/write access from the
30 /* Region 1 */
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