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/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h2 * Copyright (c) 2021-2022, Weidmueller Interface GmbH & Co. KG
3 * SPDX-License-Identifier: Apache-2.0
9 /* PHY auto-detection alias */
13 * MDC divider values
16 * divider /32 is the reset value. The network_config[mdc_clock_division]
17 * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
18 * as it claims that the MDC clock division is applied to the cpu_1x clock
21 * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK.
23 * on the UltraScale compared to the Zynq-7000.
24 * -> Contrary to earlier revisions of this driver, all dividers are available
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/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
60 k_mutex_lock(&dev_data->mutex, K_FOREVER); in mdio_xmc4xxx_transfer()
62 if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) { in mdio_xmc4xxx_transfer()
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/Zephyr-latest/boards/qemu/cortex_a9/
Dqemu_cortex_a9.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
12 model = "QEMU Cortex-A9";
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
28 compatible = "mmio-sram";
40 zephyr,shell-uart = &uart0;
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/Zephyr-latest/dts/bindings/ethernet/
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
35 The MDC clock divider for the respective GEM. This is the divider
39 Description, bits [20:18] to determine the appropriate divider for
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
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/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
86 * exhausted mid-frame
116 * Zynq-7000 TX clock configuration:
130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
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Deth_xlnx_gem.c5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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